Robert M. Ondris

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Santa Clara, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Generation of delay values for a simulation model of circuit elemen...
- Patent number 9,639,640
- Issue date May 2, 2017
- Xilinx, Inc.
- Nagaraj Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transceiver for providing a clock signal
- Patent number 9,148,192
- Issue date Sep 29, 2015
- Xilinx, Inc.
- Alan C. Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock network architecture
- Patent number 8,937,491
- Issue date Jan 20, 2015
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Preventing transistor damage
- Patent number 7,564,264
- Issue date Jul 21, 2009
- Xilinx, Inc.
- Shawn K. Morrison
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuits and methods of using parallel counter controlled delay lin...
- Patent number 7,535,278
- Issue date May 19, 2009
- Xilinx, Inc.
- Robert M. Ondris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for the main oscillator of a counter-controlled delay line
- Patent number 7,477,112
- Issue date Jan 13, 2009
- Xilinx, Inc.
- Tao Pi
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CLOCK NETWORK ARCHITECTURE
- Publication number 20140132305
- Publication date May 15, 2014
- Xilinx, Inc.
- Brian C. Gaide
- G06 - COMPUTING CALCULATING COUNTING