Robert M. Salter III

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and methods for a tamper resistant bus for secure lock bi...
- Patent number 8,803,548
- Issue date Aug 12, 2014
- Microsemi SoC Corporation
- Robert M. Salter
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Nonvolatile reprogrammable interconnect cell with FN tunneling devi...
- Patent number 6,252,273
- Issue date Jun 26, 2001
- Actel Corporation
- Robert M. Salter
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile reprogrammable interconnect cell with programmable buri...
- Patent number 6,137,728
- Issue date Oct 24, 2000
- GateField Corporation
- Jack Zezhong Peng
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile reprogrammable interconnect cell with programmable buri...
- Patent number 6,072,720
- Issue date Jun 6, 2000
- GateField Corporation
- Jack Zezhong Peng
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile reprogrammable interconnect cell with FN tunneling in s...
- Patent number 5,838,040
- Issue date Nov 17, 1998
- GateField Corporation
- Robert M. Salter
- G11 - INFORMATION STORAGE
Information Patent Grant
Floating gate FGPA cell with separated select device
- Patent number 5,773,862
- Issue date Jun 30, 1998
- Zycad Corporation
- Jack Zezhong Peng
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory control and data loading architecture for multi...
- Patent number 5,623,686
- Issue date Apr 22, 1997
- National Semiconductor Corporation
- Christopher M. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple chip package processor having feed through paths on one die
- Patent number 5,606,710
- Issue date Feb 25, 1997
- National Semiconductor Corporation
- Christopher M. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple chip processor architecture with reset intercept circuit
- Patent number 5,598,573
- Issue date Jan 28, 1997
- National Semiconductor Corporation
- Christopher M. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple chip processor architecture with memory interface control...
- Patent number 5,581,779
- Issue date Dec 3, 1996
- National Semiconductor Corporation
- Christopher M. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-system programming architecture for a multiple chip processor
- Patent number 5,566,344
- Issue date Oct 15, 1996
- National Semiconductor Corporation
- Christopher M. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Column selector circuit for shared column CMOS EPROM
- Patent number 5,359,555
- Issue date Oct 25, 1994
- National Semiconductor Corporation
- Robert M. Salter
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHODS FOR A TAMPER RESISTANT BUS FOR SECURE LOCK BI...
- Publication number 20130282943
- Publication date Oct 24, 2013
- Actel Corporation
- Robert M. Salter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY-...
- Publication number 20080137436
- Publication date Jun 12, 2008
- Actel Corporation
- Robert M. Salter
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY CELLS IN A FIELD PROGRAMMABLE GATE ARRAY
- Publication number 20080025091
- Publication date Jan 31, 2008
- Actel Corporation
- Jonathan W. Greene
- H03 - BASIC ELECTRONIC CIRCUITRY

Robert M. Salter III

Person

Patents Grantslast 30 patents

Apparatus and methods for a tamper resistant bus for secure lock bi...

Nonvolatile reprogrammable interconnect cell with FN tunneling devi...

Nonvolatile reprogrammable interconnect cell with programmable buri...

Nonvolatile reprogrammable interconnect cell with programmable buri...

Nonvolatile reprogrammable interconnect cell with FN tunneling in s...

Floating gate FGPA cell with separated select device

Non-volatile memory control and data loading architecture for multi...

Multiple chip package processor having feed through paths on one die

Multiple chip processor architecture with reset intercept circuit

Multiple chip processor architecture with memory interface control...

In-system programming architecture for a multiple chip processor

Column selector circuit for shared column CMOS EPROM

Patents Applicationslast 30 patents

APPARATUS AND METHODS FOR A TAMPER RESISTANT BUS FOR SECURE LOCK BI...

PROGRAMMING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY-...

NON-VOLATILE MEMORY CELLS IN A FIELD PROGRAMMABLE GATE ARRAY