Robert Maurice Houle

Person

Williston, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Algorithmic N search/M write ternary content addressable memory (TCAM)
- Patent number 9,859,006
- Issue date Jan 2, 2018
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Content-addressable memory having multiple reference matchlines to...
- Patent number 9,704,575
- Issue date Jul 11, 2017
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Matchline precharge architecture for self-reference matchline sensing
- Patent number 9,583,192
- Issue date Feb 28, 2017
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Majority dominant power scheme for repeated structures and structur...
- Patent number 9,172,371
- Issue date Oct 27, 2015
- GlobalFoundries U.S. 2 LLC
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Fine granularity power gating
- Patent number 8,611,169
- Issue date Dec 17, 2013
- International Business Machines Corporation
- Robert M. Houle
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems for adjusting wordline up-level voltage to impr...
- Patent number 8,582,351
- Issue date Nov 12, 2013
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Majority dominant power scheme for repeated structures and structur...
- Patent number 8,525,546
- Issue date Sep 3, 2013
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM delay circuit that tracks bitcell characteristics
- Patent number 8,233,337
- Issue date Jul 31, 2012
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM having wordline up-level voltage adjustable to assist bitcell...
- Patent number 8,228,713
- Issue date Jul 24, 2012
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power, single-ended sensing in a multi-port SRAM using pre-disc...
- Patent number 7,986,571
- Issue date Jul 26, 2011
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for calibrating internal pulses in an integrat...
- Patent number 7,973,549
- Issue date Jul 5, 2011
- International Business Machines Corporation
- Rajiv V. Joshi
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for calibrating internal pulses in an integrat...
- Patent number 7,944,229
- Issue date May 17, 2011
- International Business Machines Corporation
- Rajiv V. Joshi
- G01 - MEASURING TESTING
Information Patent Grant
Method for low power sensing in a multi-port SRAM using pre-dischar...
- Patent number 7,940,581
- Issue date May 10, 2011
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable pulsewidth and delay generating circuit for integrated...
- Patent number 7,869,302
- Issue date Jan 11, 2011
- International Business Machines Corporation
- Rajiv V. Joshi
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for low power sensing in a multi-port SRAM usi...
- Patent number 7,859,921
- Issue date Dec 28, 2010
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for low power, single-ended sensing in a multi...
- Patent number 7,830,727
- Issue date Nov 9, 2010
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable pulsewidth and delay generating circuit for integrated...
- Patent number 7,701,801
- Issue date Apr 20, 2010
- International Business Machines Corporation
- Rajiv V. Joshi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for dynamic read margin control of a memory array
- Patent number 7,042,776
- Issue date May 9, 2006
- International Business Machines Corporation
- Miles G. Canada
- G11 - INFORMATION STORAGE
Information Patent Grant
Soft fuses using bist for cache self test
- Patent number 5,835,504
- Issue date Nov 10, 1998
- International Business Machines Corporation
- David K. Balkin
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock synchronization scheme for fractional multiplication systems
- Patent number 5,691,660
- Issue date Nov 25, 1997
- International Business Machines Corporation
- Robert Edward Busch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Precise stopping of a high speed microprocessor clock
- Patent number 5,668,983
- Issue date Sep 16, 1997
- International Business Machines Corporation
- Robert Maurice Houle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital clock signal multiplier circuit
- Patent number 5,422,835
- Issue date Jun 6, 1995
- International Business Machines Corporation
- Robert M. Houle
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ALGORITHMIC N SEARCH/M WRITE TERNARY CONTENT ADDRESSABLE MEMORY (TCAM)
- Publication number 20170365341
- Publication date Dec 21, 2017
- GLOBALFOUNDRIES INC.
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
CONTENT-ADDRESSABLE MEMORY HAVING MULTIPLE REFERENCE MATCHLINES TO...
- Publication number 20170200500
- Publication date Jul 13, 2017
- GLOBALFOUNDRIES INC.
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
STATISTICAL POWER ESTIMATION
- Publication number 20150025857
- Publication date Jan 22, 2015
- International Business Machines Corporation
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAJORITY DOMINANT POWER SCHEME FOR REPEATED STRUCTURES AND STRUCTUR...
- Publication number 20130307580
- Publication date Nov 21, 2013
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
MAJORITY DOMINANT POWER SCHEME FOR REPEATED STRUCTURES AND STRUCTUR...
- Publication number 20130234754
- Publication date Sep 12, 2013
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
FINE GRANULARITY POWER GATING
- Publication number 20130148455
- Publication date Jun 13, 2013
- International Business Machines Corporation
- Robert M. Houle
- G11 - INFORMATION STORAGE
Information Patent Application
Methods and Systems for Adjusting Wordline Up-Level Voltage to Impr...
- Publication number 20120075919
- Publication date Mar 29, 2012
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM Having Wordline Up-Level Voltage Adjustable to Assist Bitcell...
- Publication number 20120075918
- Publication date Mar 29, 2012
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM DELAY CIRCUIT THAT TRACKS BITCELL CHARACTERISTICS
- Publication number 20110090750
- Publication date Apr 21, 2011
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
Low Power Sensing In a Multi-Port Sram Using Pre-Discharged Bit Lines
- Publication number 20100315894
- Publication date Dec 16, 2010
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
Low Power, Single-Ended Sensing in a Multi-Port SRAM Using Pre-Disc...
- Publication number 20100309740
- Publication date Dec 9, 2010
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRAT...
- Publication number 20090309622
- Publication date Dec 17, 2009
- Rajiv V. Joshi
- G01 - MEASURING TESTING
Information Patent Application
PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED...
- Publication number 20090303812
- Publication date Dec 10, 2009
- Rajiv V. Joshi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHOD FOR LOW POWER SENSING IN A MULTI-PORT SRAM USI...
- Publication number 20090303820
- Publication date Dec 10, 2009
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus and Method for Low Power, Single-Ended Sensing in a Multi...
- Publication number 20090303821
- Publication date Dec 10, 2009
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR...
- Publication number 20090144507
- Publication date Jun 4, 2009
- International Business Machines Corporation
- John E. Barth, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM...
- Publication number 20090144504
- Publication date Jun 4, 2009
- International Business Machines Corporation
- John E. Barth, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED...
- Publication number 20080310246
- Publication date Dec 18, 2008
- Rajiv V. Joshi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRAT...
- Publication number 20080309364
- Publication date Dec 18, 2008
- Rajiv V. Joshi
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND STRUCTURE FOR DOMINO READ BIT LINE AND SET RESET LATCH
- Publication number 20080298137
- Publication date Dec 4, 2008
- Yuen Hung Chan
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND CIRCUIT FOR DYNAMIC READ MARGIN CONTROL OF A MEMORY ARRAY
- Publication number 20050180228
- Publication date Aug 18, 2005
- International Business Machines Corporation
- Miles G. Canada
- G11 - INFORMATION STORAGE

Robert Maurice Houle

Person

Patents Grantslast 30 patents

Algorithmic N search/M write ternary content addressable memory (TCAM)

Content-addressable memory having multiple reference matchlines to...

Matchline precharge architecture for self-reference matchline sensing

Majority dominant power scheme for repeated structures and structur...

Fine granularity power gating

Methods and systems for adjusting wordline up-level voltage to impr...

Majority dominant power scheme for repeated structures and structur...

SRAM delay circuit that tracks bitcell characteristics

SRAM having wordline up-level voltage adjustable to assist bitcell...

Low power, single-ended sensing in a multi-port SRAM using pre-disc...

Method and apparatus for calibrating internal pulses in an integrat...

Method and apparatus for calibrating internal pulses in an integrat...

Method for low power sensing in a multi-port SRAM using pre-dischar...

Programmable pulsewidth and delay generating circuit for integrated...

Apparatus and method for low power sensing in a multi-port SRAM usi...

Apparatus and method for low power, single-ended sensing in a multi...

Programmable pulsewidth and delay generating circuit for integrated...

Method and circuit for dynamic read margin control of a memory array

Soft fuses using bist for cache self test

Clock synchronization scheme for fractional multiplication systems

Precise stopping of a high speed microprocessor clock

Digital clock signal multiplier circuit

Patents Applicationslast 30 patents

ALGORITHMIC N SEARCH/M WRITE TERNARY CONTENT ADDRESSABLE MEMORY (TCAM)

CONTENT-ADDRESSABLE MEMORY HAVING MULTIPLE REFERENCE MATCHLINES TO...

STATISTICAL POWER ESTIMATION

MAJORITY DOMINANT POWER SCHEME FOR REPEATED STRUCTURES AND STRUCTUR...

MAJORITY DOMINANT POWER SCHEME FOR REPEATED STRUCTURES AND STRUCTUR...

FINE GRANULARITY POWER GATING

Methods and Systems for Adjusting Wordline Up-Level Voltage to Impr...

SRAM Having Wordline Up-Level Voltage Adjustable to Assist Bitcell...

SRAM DELAY CIRCUIT THAT TRACKS BITCELL CHARACTERISTICS

Low Power Sensing In a Multi-Port Sram Using Pre-Discharged Bit Lines

Low Power, Single-Ended Sensing in a Multi-Port SRAM Using Pre-Disc...

METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRAT...

PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED...

APPARATUS AND METHOD FOR LOW POWER SENSING IN A MULTI-PORT SRAM USI...

Apparatus and Method for Low Power, Single-Ended Sensing in a Multi...

APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR...

STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM...

PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED...

METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRAT...

METHOD AND STRUCTURE FOR DOMINO READ BIT LINE AND SET RESET LATCH

METHOD AND CIRCUIT FOR DYNAMIC READ MARGIN CONTROL OF A MEMORY ARRAY