Robert N. Ehrlich

Person

Round Rock, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Debug method and device for providing indexed trace messages
- Patent number 9,626,279
- Issue date Apr 18, 2017
- NXP USA, INC.
- Robert A. McGowan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug method and device for handling exceptions and interrupts
- Patent number 9,626,280
- Issue date Apr 18, 2017
- NXP USA, INC.
- Robert N. Ehrlich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predicate trace compression
- Patent number 9,495,169
- Issue date Nov 15, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Robert N. Ehrlich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan testing with staggered clocks
- Patent number 9,366,724
- Issue date Jun 14, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Darrell L. Carder
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for multicore processing
- Patent number 9,304,880
- Issue date Apr 5, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Michael L. Olivarez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous multi-core integrated circuit and method for debuggin...
- Patent number 8,666,690
- Issue date Mar 4, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Amar Nath Deogharia
- G01 - MEASURING TESTING
Information Patent Grant
Debugger recovery on exit from low power mode
- Patent number 8,601,315
- Issue date Dec 3, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Robert Ehrlich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache result register for quick cache information lookup
- Patent number 8,572,323
- Issue date Oct 29, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Robert Ehrlich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware managed context sensitive interrupt priority level control
- Patent number 7,793,025
- Issue date Sep 7, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Robert Ehrlich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus having a dynamic timing bridge
- Patent number 7,747,889
- Issue date Jun 29, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Craig D. Shaw
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
SCAN TESTING WITH STAGGERED CLOCKS
- Publication number 20160169965
- Publication date Jun 16, 2016
- FREESCALE SEMICONDUCTOR, INC.
- DARRELL L. CARDER
- G01 - MEASURING TESTING
Information Patent Application
DEBUG METHOD AND DEVICE FOR PROVIDING INDEXED TRACE MESSAGES
- Publication number 20150006863
- Publication date Jan 1, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Robert A. McGowan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG METHOD AND DEVICE FOR HANDLING EXCEPTIONS AND INTERRUPTS
- Publication number 20150006869
- Publication date Jan 1, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Robert N. Ehrlich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MULTICORE PROCESSING
- Publication number 20140281735
- Publication date Sep 18, 2014
- Michael L. Olivarez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREDICATE TRACE COMPRESSION
- Publication number 20130283020
- Publication date Oct 24, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Robert N. Ehrlich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETEROGENEOUS MULTI-CORE INTEGRATED CIRCUIT AND METHOD FOR DEBUGGIN...
- Publication number 20130090887
- Publication date Apr 11, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Amar Nath Deogharia
- G01 - MEASURING TESTING
Information Patent Application
Cache Result Register for Quick Cache Information Lookup
- Publication number 20120173825
- Publication date Jul 5, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Robert Ehrlich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Debugger Recovery on Exit from Low Power Mode
- Publication number 20120110353
- Publication date May 3, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Robert Ehrlich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hardware Managed Context Sensitive Interrupt Priority Level Control
- Publication number 20090248935
- Publication date Oct 1, 2009
- Robert Ehrlich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUS HAVING A DYNAMIC TIMING BRIDGE
- Publication number 20080028253
- Publication date Jan 31, 2008
- Craig D. Shaw
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Robert N. Ehrlich

Person

Patents Grantslast 30 patents

Debug method and device for providing indexed trace messages

Debug method and device for handling exceptions and interrupts

Predicate trace compression

Scan testing with staggered clocks

System and method for multicore processing

Heterogeneous multi-core integrated circuit and method for debuggin...

Debugger recovery on exit from low power mode

Cache result register for quick cache information lookup

Hardware managed context sensitive interrupt priority level control

Bus having a dynamic timing bridge

Patents Applicationslast 30 patents

SCAN TESTING WITH STAGGERED CLOCKS

DEBUG METHOD AND DEVICE FOR PROVIDING INDEXED TRACE MESSAGES

DEBUG METHOD AND DEVICE FOR HANDLING EXCEPTIONS AND INTERRUPTS

SYSTEM AND METHOD FOR MULTICORE PROCESSING

PREDICATE TRACE COMPRESSION

HETEROGENEOUS MULTI-CORE INTEGRATED CIRCUIT AND METHOD FOR DEBUGGIN...

Cache Result Register for Quick Cache Information Lookup

Debugger Recovery on Exit from Low Power Mode

Hardware Managed Context Sensitive Interrupt Priority Level Control

BUS HAVING A DYNAMIC TIMING BRIDGE