Robert N. Murdoch

Person

Sacramento, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Configurable page closing method and apparatus for multi-port host...
- Patent number 6,370,624
- Issue date Apr 9, 2002
- Intel Corporation
- Jasmin Ajanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Achieving page hit memory cycles on a virtual address reference
- Patent number 6,226,730
- Issue date May 1, 2001
- Intel Corporation
- Robert N. Murdoch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for storing a device row indicator for use in...
- Patent number 6,199,151
- Issue date Mar 6, 2001
- Intel Corporation
- Michael W. Williams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable page closing method and apparatus for multi-port host...
- Patent number 6,199,145
- Issue date Mar 6, 2001
- Intel Corporation
- Jasmin Ajanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for addressing a memory resource comprising me...
- Patent number 6,154,825
- Issue date Nov 28, 2000
- Intel Corporation
- Robert N. Murdoch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for enabling multi-bit counter values to reliably cross b...
- Patent number 5,894,567
- Issue date Apr 13, 1999
- Intel Corporation
- James M. Dodd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for the detection of reordering hazards
- Patent number 5,889,974
- Issue date Mar 30, 1999
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for sampling data from a memory
- Patent number 5,860,128
- Issue date Jan 12, 1999
- Intel Corporation
- Robert N. Murdoch
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for quickly transferring data from a first bus...
- Patent number 5,857,082
- Issue date Jan 5, 1999
- Intel Corporation
- Robert N. Murdoch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamically deferring transactions
- Patent number 5,761,444
- Issue date Jun 2, 1998
- Intel Corporation
- Jasmin Ajanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory configuration decoding system having automatic row base addr...
- Patent number 5,572,692
- Issue date Nov 5, 1996
- Intel Corporation
- Robert N. Murdoch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with integrated delay line circuitry
- Patent number 5,276,858
- Issue date Jan 4, 1994
- Intel Corporation
- Jayawant V. Oak
- G11 - INFORMATION STORAGE
Information Patent Grant
Data processing system having unique multilevel microcode architecture
- Patent number 4,901,235
- Issue date Feb 13, 1990
- Data General Corporation
- Chandra R. Vora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Content addressable memory and self-blocking driver
- Patent number 4,858,180
- Issue date Aug 15, 1989
- Data General Corporation
- Robert Murdoch
- G11 - INFORMATION STORAGE
Information Patent Grant
Carry-save propagate adder
- Patent number 4,718,034
- Issue date Jan 5, 1988
- Data General Corporation
- Nabil Takla
- G06 - COMPUTING CALCULATING COUNTING

Robert N. Murdoch

Person

Patents Grantslast 30 patents

Configurable page closing method and apparatus for multi-port host...

Achieving page hit memory cycles on a virtual address reference

Apparatus and method for storing a device row indicator for use in...

Configurable page closing method and apparatus for multi-port host...

Method and apparatus for addressing a memory resource comprising me...

Mechanism for enabling multi-bit counter values to reliably cross b...

Method and apparatus for the detection of reordering hazards

Method and apparatus for sampling data from a memory

Method and apparatus for quickly transferring data from a first bus...

Method and apparatus for dynamically deferring transactions

Memory configuration decoding system having automatic row base addr...

Memory controller with integrated delay line circuitry

Data processing system having unique multilevel microcode architecture

Content addressable memory and self-blocking driver

Carry-save propagate adder