Robert Paul Kurshan

Person

New York, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for performing verification of an electronic design
- Patent number 9,047,427
- Issue date Jun 2, 2015
- Cadence Design Systems, Inc.
- Frederic Doucet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing top down design and verification...
- Patent number 8,539,405
- Issue date Sep 17, 2013
- Cadence Design Systems, Inc.
- Robert P. Kurshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing top down design and verification...
- Patent number 8,234,609
- Issue date Jul 31, 2012
- Cadence Design Systems, Inc.
- Robert P. Kurshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing top down design and verification...
- Patent number 7,937,673
- Issue date May 3, 2011
- Cadence Design Systems, Inc.
- Robert P. Kurshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coverage metric and coverage computation for verification based on...
- Patent number 7,712,059
- Issue date May 4, 2010
- Cadence Design Systems, Inc.
- Xiaoqun Du
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for verifying circuit designs through propagation...
- Patent number 7,444,274
- Issue date Oct 28, 2008
- Cadence Design Systems, Inc.
- Manu Chopra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coverage metric and coverage computation for verification based on...
- Patent number 7,181,708
- Issue date Feb 20, 2007
- Cadence Design Systems, Inc.
- Xiaoqun Du
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for partitioning an integrated circuit design
- Patent number 7,047,510
- Issue date May 16, 2006
- Cadence Design Systems, Inc.
- Manu Chopra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification coverage method
- Patent number 6,708,143
- Issue date Mar 16, 2004
- Lucent Technologies Inc.
- Robert Paul Kurshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for identifying cyclicity in circuit designs
- Patent number 6,591,231
- Issue date Jul 8, 2003
- Agere Systems Inc.
- Robert Paul Kurshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detecting of model errors through simplification of model via state...
- Patent number 6,311,293
- Issue date Oct 30, 2001
- Lucent Technologies Inc.
- Robert Paul Kurshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static partial order reduction
- Patent number 6,295,515
- Issue date Sep 25, 2001
- Lucent Technologies Inc.
- Robert Paul Kurshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying hardware in its software context and vice-versa
- Patent number 6,209,120
- Issue date Mar 27, 2001
- Lucent Technologies, Inc.
- Robert Paul Kurshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automata-theoretic verification of systems
- Patent number 6,185,516
- Issue date Feb 6, 2001
- Lucent Technologies Inc.
- Ronald H. Hardin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification tool computation reduction
- Patent number 6,102,959
- Issue date Aug 15, 2000
- Lucent Technologies Inc.
- Ronald H. Hardin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constraint validity checking
- Patent number 6,099,575
- Issue date Aug 8, 2000
- Lucent Technologies Inc.
- Ronald H. Hardin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for defining properties in finite-state machines
- Patent number 5,966,516
- Issue date Oct 12, 1999
- Lucent Technologies Inc.
- Gary F. De Palma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for detecting errors in models through restriction
- Patent number 5,946,481
- Issue date Aug 31, 1999
- Lucent Technologies Inc.
- Robert Paul Kurshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient regression verification
- Patent number 5,926,622
- Issue date Jul 20, 1999
- Lucent Technologies Inc.
- Ronald H. Hardin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for detecting errors in models through restriction
- Patent number 5,901,073
- Issue date May 4, 1999
- Lucent Technologies Inc.
- Robert Paul Kurshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification of homomorphism between two system models
- Patent number 5,740,084
- Issue date Apr 14, 1998
- Lucent Technologies Inc.
- Ronald H. Hardin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deriving tractable sub-system for model of larger system
- Patent number 5,691,925
- Issue date Nov 25, 1997
- Lucent Technologies Inc.
- Ronald H. Hardin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing verification by successive approximation
- Patent number 5,483,470
- Issue date Jan 9, 1996
- AT&T Corp.
- Rajeev Alur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analytical development and verification of control-intensive systems
- Patent number 5,163,016
- Issue date Nov 10, 1992
- AT&T Bell Laboratories
- Zvi Har'El
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple tone detector and locator
- Patent number 4,361,875
- Issue date Nov 30, 1982
- Bell Telephone Laboratories, Incorporated
- David Hertz
- G01 - MEASURING TESTING
Information Patent Grant
Cyclotomic tone detector and locator
- Patent number 4,348,735
- Issue date Sep 7, 1982
- Bell Telephone Laboratories, Incorporated
- David Hertz
- G01 - MEASURING TESTING
Information Patent Grant
Broadband cyclotomic tone detector
- Patent number 4,333,156
- Issue date Jun 1, 1982
- Bell Telephone Laboratories, Incorporated
- Robert P. Kurshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recursive detector-oscillator circuit
- Patent number 3,971,998
- Issue date Jul 27, 1976
- Bell Telephone Laboratories, Incorporated
- Bhaskarpillai Gopinath
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Periodic sequence generators using ordinary arithmetic
- Patent number 3,963,905
- Issue date Jun 15, 1976
- Bell Telephone Laboratories, Incorporated
- Bhaskarpillai Gopinath
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR IMPLEMENTING TOP DOWN DESIGN AND VERIFICATION...
- Publication number 20120311513
- Publication date Dec 6, 2012
- Cadence Design Systems, Inc.
- Robert P. Kurshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Implementing Top Down Design and Verification...
- Publication number 20090164968
- Publication date Jun 25, 2009
- Cadence Design Systems, Inc.
- Robert P. Kurshan
- G06 - COMPUTING CALCULATING COUNTING

Robert Paul Kurshan

Person

Patents Grantslast 30 patents

Method and system for performing verification of an electronic design

Method and system for implementing top down design and verification...

Method and system for implementing top down design and verification...

Method and system for implementing top down design and verification...

Coverage metric and coverage computation for verification based on...

Method and system for verifying circuit designs through propagation...

Coverage metric and coverage computation for verification based on...

Method and system for partitioning an integrated circuit design

Verification coverage method

Method for identifying cyclicity in circuit designs

Detecting of model errors through simplification of model via state...

Static partial order reduction

Verifying hardware in its software context and vice-versa

Automata-theoretic verification of systems

Verification tool computation reduction

Constraint validity checking

Apparatus for defining properties in finite-state machines

Method for detecting errors in models through restriction

Efficient regression verification

Method for detecting errors in models through restriction

Verification of homomorphism between two system models

Deriving tractable sub-system for model of larger system

Timing verification by successive approximation

Analytical development and verification of control-intensive systems

Multiple tone detector and locator

Cyclotomic tone detector and locator

Broadband cyclotomic tone detector

Recursive detector-oscillator circuit

Periodic sequence generators using ordinary arithmetic

Patents Applicationslast 30 patents

METHOD AND SYSTEM FOR IMPLEMENTING TOP DOWN DESIGN AND VERIFICATION...

Method and System for Implementing Top Down Design and Verification...