Robert T. Golla

Person

Round Rock, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Load-store unit dual tags and replays
- Patent number 11,983,538
- Issue date May 14, 2024
- Cadence Design Systems, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing multiple cache memory circuit operations
- Patent number 11,960,400
- Issue date Apr 16, 2024
- Cadence Design Systems, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction error handling
- Patent number 11,740,973
- Issue date Aug 29, 2023
- Cadence Design Systems, Inc.
- Matthew B. Smittle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Removal of dependent instructions from an execution pipeline
- Patent number 11,656,876
- Issue date May 23, 2023
- Cadence Design Systems, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forced debug mode entry
- Patent number 11,537,505
- Issue date Dec 27, 2022
- Cadence Design Systems, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Program thread selection between a plurality of execution pipelines
- Patent number 11,531,550
- Issue date Dec 20, 2022
- Cadence Design Systems, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for fast interrupt handling
- Patent number 11,507,414
- Issue date Nov 22, 2022
- Cadence Design Systems, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed fairness protocol for interconnect networks
- Patent number 11,126,577
- Issue date Sep 21, 2021
- Oracle International Corporation
- Robert Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug command execution using existing datapath circuitry
- Patent number 11,119,149
- Issue date Sep 14, 2021
- Western Digital Technologies, Inc.
- Deepak Panwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Illegal instruction exception handling
- Patent number 11,086,631
- Issue date Aug 10, 2021
- Western Digital Technologies, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache diagnostic techniques
- Patent number 11,023,342
- Issue date Jun 1, 2021
- Western Digital Technologies, Inc.
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-threaded instruction buffer design
- Patent number 10,860,326
- Issue date Dec 8, 2020
- Oracle International Corporation
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Run-length encoding decompression
- Patent number 10,534,606
- Issue date Jan 14, 2020
- Oracle International Corporation
- Jeffrey S. Brooks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed fairness protocol for interconnect networks
- Patent number 10,474,601
- Issue date Nov 12, 2019
- Oracle International Corporation
- Robert Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing thread selection at fetch, select, and commit stages of...
- Patent number 10,430,342
- Issue date Oct 1, 2019
- Oracle International Corporation
- Yuan Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-threaded instruction buffer design
- Patent number 10,346,173
- Issue date Jul 9, 2019
- Oracle International Corporation
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive microprocessor power ramp control
- Patent number 9,710,042
- Issue date Jul 18, 2017
- Oracle International Corporation
- Haowei Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for out-of-order resource allocation and dealloca...
- Patent number 9,690,625
- Issue date Jun 27, 2017
- Oracle America, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Precise excecution of versioned store instructions
- Patent number 9,672,298
- Issue date Jun 6, 2017
- Oracle International Corporation
- Zoran Radovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mitigation of thread hogs on a threaded processor and prevention of...
- Patent number 9,665,375
- Issue date May 30, 2017
- Oracle International Corporation
- Yuan C. Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single cycle data movement between general purpose and floating-poi...
- Patent number 9,304,767
- Issue date Apr 5, 2016
- Oracle America, Inc.
- Christopher Olson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimal deallocation of instructions from a unified pick queue
- Patent number 9,286,075
- Issue date Mar 15, 2016
- Oracle America, Inc.
- Matthew B. Smittle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dependency matrix for the determination of load dependencies
- Patent number 9,262,171
- Issue date Feb 16, 2016
- Oracle America, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for balancing instruction loads between multiple...
- Patent number 9,122,487
- Issue date Sep 1, 2015
- Oracle America, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified high-frequency out-of-order pick queue with support for tri...
- Patent number 9,058,180
- Issue date Jun 16, 2015
- Oracle America, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Perceptron-based branch prediction mechanism for predicting conditi...
- Patent number 8,904,156
- Issue date Dec 2, 2014
- Oracle America, Inc.
- Manish K. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor and method for implementing instruction support for hash...
- Patent number 8,832,464
- Issue date Sep 9, 2014
- Oracle America, Inc.
- Christopher H. Olson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Mechanism for selecting instructions for execution in a multithread...
- Patent number 8,769,246
- Issue date Jul 1, 2014
- Open Computing Trust I & II
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread fairness on a multi-threaded processor with multi-cycle cryp...
- Patent number 8,560,814
- Issue date Oct 15, 2013
- Oracle International Corporation
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor operating mode for mitigating dependency conditions betwe...
- Patent number 8,504,805
- Issue date Aug 6, 2013
- Oracle America, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Technique for Overriding Memory Attributes
- Publication number 20230350805
- Publication date Nov 2, 2023
- Cadence Design Systems, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Queue Circuit For Controlling Access To A Memory Circuit
- Publication number 20230350605
- Publication date Nov 2, 2023
- Cadence Design Systems, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing Multiple Cache Memory Circuit Operations
- Publication number 20230342296
- Publication date Oct 26, 2023
- Cadence Design Systems, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Load-Store Unit Dual Tags and Replays
- Publication number 20230333856
- Publication date Oct 19, 2023
- Cadence Design Systems, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit for Fast Interrupt Handling
- Publication number 20220164220
- Publication date May 26, 2022
- Western Digital Technologies, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction Error Handling
- Publication number 20220164254
- Publication date May 26, 2022
- Western Digital Technologies, Inc.
- Matthew B. Smittle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Program Thread Selection Between a Plurality of Execution Pipelines
- Publication number 20220137973
- Publication date May 5, 2022
- Western Digital Technologies, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Removal of Dependent Instructions from an Execution Pipeline
- Publication number 20220137976
- Publication date May 5, 2022
- Western Digital Technologies, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Forced Debug Mode Entry
- Publication number 20220121557
- Publication date Apr 21, 2022
- Western Digital Technologies, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE DIAGNOSTIC TECHNIQUES
- Publication number 20200174903
- Publication date Jun 4, 2020
- Western Digital Technologies, Inc.
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG COMMAND EXECUTION USING EXISTING DATAPATH CIRCUITRY
- Publication number 20200174071
- Publication date Jun 4, 2020
- Western Digital Technologies, Inc.
- Deepak Panwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ILLEGAL INSTRUCTION EXCEPTION HANDLING
- Publication number 20200174794
- Publication date Jun 4, 2020
- Western Digital Technologies, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED FAIRNESS PROTOCOL FOR INTERCONNECT NETWORKS
- Publication number 20200073835
- Publication date Mar 5, 2020
- Robert Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-THREADED INSTRUCTION BUFFER DESIGN
- Publication number 20200004549
- Publication date Jan 2, 2020
- ORACLE INTERNATIONAL CORPORATION
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED FAIRNESS PROTOCOL FOR INTERCONNECT NETWORKS
- Publication number 20180225239
- Publication date Aug 9, 2018
- Robert Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING THREAD SELECTION AT FETCH, SELECT, AND COMMIT STAGES OF...
- Publication number 20170139706
- Publication date May 18, 2017
- Oracle International Corporation
- Yuan Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE MICROPROCESSOR POWER RAMP CONTROL
- Publication number 20160048187
- Publication date Feb 18, 2016
- Oracle International Corporation
- Haowei Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Run-Length Encoding Decompression
- Publication number 20160019064
- Publication date Jan 21, 2016
- ORACLE INTERNATIONAL CORPORATION
- JEFFREY S. BROOKS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRECISE EXCECUTION OF VERSIONED STORE INSTRUCTIONS
- Publication number 20150317338
- Publication date Nov 5, 2015
- ORACLE INTERNATIONAL CORPORATION
- Zoran Radovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATION OF THREAD HOGS ON A THREADED PROCESSOR USING A GENERAL L...
- Publication number 20130297910
- Publication date Nov 7, 2013
- Jared C. Smolens
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATION OF THREAD HOGS ON A THREADED PROCESSOR
- Publication number 20130290675
- Publication date Oct 31, 2013
- Yuan C. Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-THREADED INSTRUCTION BUFFER DESIGN
- Publication number 20120233441
- Publication date Sep 13, 2012
- Jama I. Barreh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD FAIRNESS ON A MULTI-THREADED PROCESSOR WITH MULTI-CYCLE CRYP...
- Publication number 20110276783
- Publication date Nov 10, 2011
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR SELECTING INSTRUCTIONS FOR EXECUTION IN A MULTITHREAD...
- Publication number 20110138153
- Publication date Jun 9, 2011
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR LOCAL OPERAND BYPASSING FOR CRYPTOGRAPHIC...
- Publication number 20110087895
- Publication date Apr 14, 2011
- Christopher H. Olson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERCEPTRON-BASED BRANCH PREDICTION MECHANISM FOR PREDICTING CONDITI...
- Publication number 20110087866
- Publication date Apr 14, 2011
- Manish K. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPORTED REGISTER FILE FOR MULTITHREADED PROCESSORS AND PROCESSO...
- Publication number 20110078414
- Publication date Mar 31, 2011
- Christopher H. Olson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMAL DEALLOCATION OF INSTRUCTIONS FROM A UNIFIED PICK QUEUE
- Publication number 20110078697
- Publication date Mar 31, 2011
- Matthew B. Smittle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MITIGATION OF THREAD HOGS ON A THREADED PROCESSOR
- Publication number 20110029978
- Publication date Feb 3, 2011
- Jared C. Smolens
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIFIED HIGH-FREQUENCY OUT-OF-ORDER PICK QUEUE WITH SUPPORT FOR SPE...
- Publication number 20100332804
- Publication date Dec 30, 2010
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING

Robert T. Golla

Person

Patents Grantslast 30 patents

Load-store unit dual tags and replays

Managing multiple cache memory circuit operations

Instruction error handling

Removal of dependent instructions from an execution pipeline

Forced debug mode entry

Program thread selection between a plurality of execution pipelines

Circuit for fast interrupt handling

Distributed fairness protocol for interconnect networks

Debug command execution using existing datapath circuitry

Illegal instruction exception handling

Cache diagnostic techniques

Multi-threaded instruction buffer design

Run-length encoding decompression

Distributed fairness protocol for interconnect networks

Optimizing thread selection at fetch, select, and commit stages of...

Multi-threaded instruction buffer design

Adaptive microprocessor power ramp control

System and method for out-of-order resource allocation and dealloca...

Precise excecution of versioned store instructions

Mitigation of thread hogs on a threaded processor and prevention of...

Single cycle data movement between general purpose and floating-poi...

Optimal deallocation of instructions from a unified pick queue

Dependency matrix for the determination of load dependencies

System and method for balancing instruction loads between multiple...

Unified high-frequency out-of-order pick queue with support for tri...

Perceptron-based branch prediction mechanism for predicting conditi...

Processor and method for implementing instruction support for hash...

Mechanism for selecting instructions for execution in a multithread...

Thread fairness on a multi-threaded processor with multi-cycle cryp...

Processor operating mode for mitigating dependency conditions betwe...

Patents Applicationslast 30 patents

Technique for Overriding Memory Attributes

Queue Circuit For Controlling Access To A Memory Circuit

Managing Multiple Cache Memory Circuit Operations

Load-Store Unit Dual Tags and Replays

Circuit for Fast Interrupt Handling

Instruction Error Handling

Program Thread Selection Between a Plurality of Execution Pipelines

Removal of Dependent Instructions from an Execution Pipeline

Forced Debug Mode Entry

CACHE DIAGNOSTIC TECHNIQUES

DEBUG COMMAND EXECUTION USING EXISTING DATAPATH CIRCUITRY

ILLEGAL INSTRUCTION EXCEPTION HANDLING

DISTRIBUTED FAIRNESS PROTOCOL FOR INTERCONNECT NETWORKS

MULTI-THREADED INSTRUCTION BUFFER DESIGN

DISTRIBUTED FAIRNESS PROTOCOL FOR INTERCONNECT NETWORKS

OPTIMIZING THREAD SELECTION AT FETCH, SELECT, AND COMMIT STAGES OF...

ADAPTIVE MICROPROCESSOR POWER RAMP CONTROL

Run-Length Encoding Decompression

PRECISE EXCECUTION OF VERSIONED STORE INSTRUCTIONS

MITIGATION OF THREAD HOGS ON A THREADED PROCESSOR USING A GENERAL L...

MITIGATION OF THREAD HOGS ON A THREADED PROCESSOR

MULTI-THREADED INSTRUCTION BUFFER DESIGN

THREAD FAIRNESS ON A MULTI-THREADED PROCESSOR WITH MULTI-CYCLE CRYP...

MECHANISM FOR SELECTING INSTRUCTIONS FOR EXECUTION IN A MULTITHREAD...

APPARATUS AND METHOD FOR LOCAL OPERAND BYPASSING FOR CRYPTOGRAPHIC...

PERCEPTRON-BASED BRANCH PREDICTION MECHANISM FOR PREDICTING CONDITI...

MULTIPORTED REGISTER FILE FOR MULTITHREADED PROCESSORS AND PROCESSO...

OPTIMAL DEALLOCATION OF INSTRUCTIONS FROM A UNIFIED PICK QUEUE

DYNAMIC MITIGATION OF THREAD HOGS ON A THREADED PROCESSOR

UNIFIED HIGH-FREQUENCY OUT-OF-ORDER PICK QUEUE WITH SUPPORT FOR SPE...