Robert W. Moss

Person

Longmont, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Data storage system data access arbitration
- Patent number 11,481,342
- Issue date Oct 25, 2022
- Seagate Technology LLC
- Robert Wayne Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Jitter attack protection circuit
- Patent number 11,308,239
- Issue date Apr 19, 2022
- Seagate Technology LLC
- Robert Wayne Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encrypting system level data structures
- Patent number 11,210,406
- Issue date Dec 28, 2021
- Seagate Technology LLC
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual controller memory buffer
- Patent number 11,157,212
- Issue date Oct 26, 2021
- Seagate Technology, LLC
- Robert Wayne Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage compute appliance with internal data encryption
- Patent number 11,017,127
- Issue date May 25, 2021
- Seagate Technology LLC
- Stacey Secatch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage compute appliance with user authentication and memory alloc...
- Patent number 10,909,272
- Issue date Feb 2, 2021
- Seagate Technology LLC
- Dana Lynn Simonson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced garbage collection
- Patent number 10,739,996
- Issue date Aug 11, 2020
- Seagate Technology LLC
- David Scott Ebsen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encryption key shredding to protect non-persistent data
- Patent number 10,715,509
- Issue date Jul 14, 2020
- Seagate Technology LLC
- Stacey Secatch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced read recovery based on write time information
- Patent number 10,289,305
- Issue date May 14, 2019
- Seagate Technology LLC
- Dana L. Simonson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Random time generated interrupts in a cryptographic hardware pipeli...
- Patent number 10,270,586
- Issue date Apr 23, 2019
- Seagate Technology LLC
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hash authenticated data
- Patent number 10,211,976
- Issue date Feb 19, 2019
- Seagate Technology LLC
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encryption key shredding to protect non-persistent data
- Patent number 10,142,304
- Issue date Nov 27, 2018
- Seagate Technology LLC
- Stacey Secatch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced read recovery based on write time information
- Patent number 9,977,597
- Issue date May 22, 2018
- Seagate Technology LLC
- Dana L. Simonson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for securing communications ports in an electr...
- Patent number 7,363,564
- Issue date Apr 22, 2008
- Seagate Technology LLC
- Robert Wayne Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look ahead split release for a data bus
- Patent number 7,174,401
- Issue date Feb 6, 2007
- LSI Logic Corporation
- Russell B. Stuber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Long path at-speed testing
- Patent number 7,065,683
- Issue date Jun 20, 2006
- LSI Logic Corporation
- David O. Sluiter
- G01 - MEASURING TESTING
Information Patent Grant
Methods and structure for preserving lock signals on multiple buses...
- Patent number 7,013,356
- Issue date Mar 14, 2006
- LSI Logic Corporation
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data ready indicator between different clock domains
- Patent number 6,999,542
- Issue date Feb 14, 2006
- LSI Logic Corporation
- Peter Korger
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and structure for dynamic modifications to arbitration for...
- Patent number 6,985,985
- Issue date Jan 10, 2006
- LSI Logic Corporation
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for arbitrating non-queued split master devices on a data...
- Patent number 6,948,019
- Issue date Sep 20, 2005
- LSI Logic Corporation
- Russell B. Stuber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for flushing slave transactions from resetting masters of...
- Patent number 6,938,113
- Issue date Aug 30, 2005
- LSI Logic Corporation
- Russell B. Stuber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller and method of aligning write data to a memory device
- Patent number 6,917,561
- Issue date Jul 12, 2005
- LSI Logic Corporation
- Robert W. Moss
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic command buffer for a slave device on a data bus
- Patent number 6,910,087
- Issue date Jun 21, 2005
- LSI Logic Corporation
- Russell B. Stuber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and structure for state preservation to improve fairness in...
- Patent number 6,907,491
- Issue date Jun 14, 2005
- LSI Logic Corporation
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and structure for using a memory model for efficient arbitr...
- Patent number 6,892,289
- Issue date May 10, 2005
- LSI Logic Corporation
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced bus architecture for posted read operation between masters...
- Patent number 6,807,593
- Issue date Oct 19, 2004
- LSI Logic Corporation
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical linearity test for integrated circuit delay lines
- Patent number 6,798,186
- Issue date Sep 28, 2004
- LSI Logic Corporation
- Peter Korger
- G01 - MEASURING TESTING
Information Patent Grant
Structure and methods for measurement of arbitration performance
- Patent number 6,741,096
- Issue date May 25, 2004
- LSI Logic Corporation
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DEBUG mode for a data bus
- Patent number 6,725,306
- Issue date Apr 20, 2004
- LSI Logic Corporation
- Russell B. Stuber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and structure for read data synchronization with minimal la...
- Patent number 6,646,929
- Issue date Nov 11, 2003
- LSI Logic Corporation
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DETERMINISTIC ALLOCATION OF SHARED RESOURCES
- Publication number 20210191752
- Publication date Jun 24, 2021
- SEAGATE TECHNOLOGY LLC
- Robert Wayne Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL CONTROLLER MEMORY BUFFER
- Publication number 20210191657
- Publication date Jun 24, 2021
- SEAGATE TECHNOLOGY LLC
- Robert Wayne Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA STORAGE SYSTEM DATA ACCESS ARBITRATION
- Publication number 20200409874
- Publication date Dec 31, 2020
- SEAGATE TECHNOLOGY LLC
- Robert Wayne Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
JITTER ATTACK PROTECTION CIRCUIT
- Publication number 20190303624
- Publication date Oct 3, 2019
- SEAGATE TECHNOLOGY LLC
- Robert Wayne Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Storage Compute Appliance with Internal Data Encryption
- Publication number 20190236318
- Publication date Aug 1, 2019
- Seagate Technology LLC
- Stacey Secatch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Storage Compute Appliance with User Authentication and Memory Alloc...
- Publication number 20190236317
- Publication date Aug 1, 2019
- Seagate Technology LLC
- Dana Lynn Simonson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENCRYPTION KEY SHREDDING TO PROTECT NON-PERSISTENT DATA
- Publication number 20190075090
- Publication date Mar 7, 2019
- SEAGATE TECHNOLOGY LLC
- Stacey Secatch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RANDOM TIME GENERATED INTERRUPTS IN A CRYPTOGRAPHIC HARDWARE PIPELI...
- Publication number 20180307864
- Publication date Oct 25, 2018
- Seagate Technology, LLC
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCED READ RECOVERY BASED ON WRITE TIME INFORMATION
- Publication number 20180253235
- Publication date Sep 6, 2018
- SEAGATE TECHNOLOGY LLC
- Dana L. Simonson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-USER DYNAMIC STORAGE ALLOCATION AND ENCRYPTION
- Publication number 20180088846
- Publication date Mar 29, 2018
- Seagate Technology LLC
- Stacey Secatch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENCRYPTION KEY SHREDDING TO PROTECT NON-PERSISTENT DATA
- Publication number 20180063102
- Publication date Mar 1, 2018
- SEAGATE TECHNOLOGY LLC
- Stacey Secatch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HASH AUTHENTICATED DATA
- Publication number 20180019876
- Publication date Jan 18, 2018
- SEAGATE TECHNOLOGY LLC
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENCRYPTING SYSTEM LEVEL DATA STRUCTURES
- Publication number 20180018469
- Publication date Jan 18, 2018
- SEAGATE TECHNOLOGY LLC
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCED READ RECOVERY BASED ON WRITE TIME INFORMATION
- Publication number 20170329525
- Publication date Nov 16, 2017
- SEAGATE TECHNOLOGY LLC
- Dana L. Simonson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hard disc streaming cryptographic operations with embedded authenti...
- Publication number 20080072071
- Publication date Mar 20, 2008
- Seagate Technology LLC
- Monty Aaron Forehand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for securing communications ports in an electr...
- Publication number 20070033454
- Publication date Feb 8, 2007
- Seagate Technology LLC
- Robert Wayne Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and structure for scan testing of secure systems
- Publication number 20050066189
- Publication date Mar 24, 2005
- Robert Moss
- G01 - MEASURING TESTING
Information Patent Application
Look ahead split release for a data bus
- Publication number 20040267992
- Publication date Dec 30, 2004
- Russell B. Stuber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and structure for preserving lock signals on multiple buses...
- Publication number 20040044813
- Publication date Mar 4, 2004
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and structure for using a memory model for efficient arbitr...
- Publication number 20040006666
- Publication date Jan 8, 2004
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Structure and methods for measurement of arbitration performance
- Publication number 20040004495
- Publication date Jan 8, 2004
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and structure for hiding DRAM bank precharge and activate l...
- Publication number 20040006665
- Publication date Jan 8, 2004
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic command buffer for a slave device on a data bus
- Publication number 20030229741
- Publication date Dec 11, 2003
- Russell B. Stuber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and structure for state preservation to improve fairness in...
- Publication number 20030229742
- Publication date Dec 11, 2003
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and structure for dynamic modifications to arbitration for...
- Publication number 20030229744
- Publication date Dec 11, 2003
- Robert W. Moss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus for flushing slave transactions from resetting masters of...
- Publication number 20030217209
- Publication date Nov 20, 2003
- Russell B. Stuber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Physical linearity test for integrated circuit delay lines
- Publication number 20030210030
- Publication date Nov 13, 2003
- Peter Korger
- G01 - MEASURING TESTING
Information Patent Application
Memory controller and method of aligning write data to a memory device
- Publication number 20030204763
- Publication date Oct 30, 2003
- Robert W. Moss
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus for arbitrating non-queued split master devices on a data...
- Publication number 20030204663
- Publication date Oct 30, 2003
- Russell B. Stuber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBUG mode for a data bus
- Publication number 20030163613
- Publication date Aug 28, 2003
- Russell B. Stuber
- G06 - COMPUTING CALCULATING COUNTING

Robert W. Moss

Person

Patents Grantslast 30 patents

Data storage system data access arbitration

Jitter attack protection circuit

Encrypting system level data structures

Virtual controller memory buffer

Storage compute appliance with internal data encryption

Storage compute appliance with user authentication and memory alloc...

Enhanced garbage collection

Encryption key shredding to protect non-persistent data

Enhanced read recovery based on write time information

Random time generated interrupts in a cryptographic hardware pipeli...

Hash authenticated data

Encryption key shredding to protect non-persistent data

Enhanced read recovery based on write time information

Method and apparatus for securing communications ports in an electr...

Look ahead split release for a data bus

Long path at-speed testing

Methods and structure for preserving lock signals on multiple buses...

Data ready indicator between different clock domains

Methods and structure for dynamic modifications to arbitration for...

Apparatus for arbitrating non-queued split master devices on a data...

Apparatus for flushing slave transactions from resetting masters of...

Memory controller and method of aligning write data to a memory device

Dynamic command buffer for a slave device on a data bus

Methods and structure for state preservation to improve fairness in...

Methods and structure for using a memory model for efficient arbitr...

Enhanced bus architecture for posted read operation between masters...

Physical linearity test for integrated circuit delay lines

Structure and methods for measurement of arbitration performance

DEBUG mode for a data bus

Methods and structure for read data synchronization with minimal la...

Patents Applicationslast 30 patents

DETERMINISTIC ALLOCATION OF SHARED RESOURCES

VIRTUAL CONTROLLER MEMORY BUFFER

DATA STORAGE SYSTEM DATA ACCESS ARBITRATION

JITTER ATTACK PROTECTION CIRCUIT

Storage Compute Appliance with Internal Data Encryption

Storage Compute Appliance with User Authentication and Memory Alloc...

ENCRYPTION KEY SHREDDING TO PROTECT NON-PERSISTENT DATA

RANDOM TIME GENERATED INTERRUPTS IN A CRYPTOGRAPHIC HARDWARE PIPELI...

ENHANCED READ RECOVERY BASED ON WRITE TIME INFORMATION

MULTI-USER DYNAMIC STORAGE ALLOCATION AND ENCRYPTION

ENCRYPTION KEY SHREDDING TO PROTECT NON-PERSISTENT DATA

HASH AUTHENTICATED DATA

ENCRYPTING SYSTEM LEVEL DATA STRUCTURES

ENHANCED READ RECOVERY BASED ON WRITE TIME INFORMATION

Hard disc streaming cryptographic operations with embedded authenti...

Method and apparatus for securing communications ports in an electr...

Methods and structure for scan testing of secure systems

Look ahead split release for a data bus

Methods and structure for preserving lock signals on multiple buses...

Methods and structure for using a memory model for efficient arbitr...

Structure and methods for measurement of arbitration performance

Methods and structure for hiding DRAM bank precharge and activate l...

Dynamic command buffer for a slave device on a data bus

Methods and structure for state preservation to improve fairness in...

Methods and structure for dynamic modifications to arbitration for...

Apparatus for flushing slave transactions from resetting masters of...

Physical linearity test for integrated circuit delay lines

Memory controller and method of aligning write data to a memory device

Apparatus for arbitrating non-queued split master devices on a data...

DEBUG mode for a data bus