Robert Walker

Person

Boulder, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods for incremental circuit design legalization during physical...
- Patent number 10,339,241
- Issue date Jul 2, 2019
- Altera Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retiming with fixed power-up states
- Patent number 10,296,701
- Issue date May 21, 2019
- Altera Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retiming with programmable power-up states
- Patent number 10,255,404
- Issue date Apr 9, 2019
- Altera Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit retiming with selective modeling of flip-flop se...
- Patent number 10,162,918
- Issue date Dec 25, 2018
- Altera Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look-up based buffer tree synthesis
- Patent number 9,189,583
- Issue date Nov 17, 2015
- Synopsys, Inc.
- Sanjay Dhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Progressive circuit evaluation for circuit optimization
- Patent number 8,621,408
- Issue date Dec 31, 2013
- Synopsys, Inc.
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delta-slack propagation for circuit optimization
- Patent number 8,578,321
- Issue date Nov 5, 2013
- Synopsys, Inc.
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zone-based area recovery in electronic design automation
- Patent number 8,527,927
- Issue date Sep 3, 2013
- Synopsys, Inc.
- Robert Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zone-based optimization framework for performing timing and design...
- Patent number 8,418,116
- Issue date Apr 9, 2013
- Synopsys, Inc.
- Robert Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Density-based area recovery in electronic design automation
- Patent number 8,266,570
- Issue date Sep 11, 2012
- Synopsys, Inc.
- Robert Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic design automation system and methods utilizing groups of...
- Patent number 6,539,536
- Issue date Mar 25, 2003
- Synopsys, Inc.
- Harbinder Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical scan architecture for design for test applications
- Patent number 6,106,568
- Issue date Aug 22, 2000
- Synopsys, Inc.
- James Beausang
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for performing partial unscan and near full sc...
- Patent number 6,067,650
- Issue date May 23, 2000
- Synopsys, Inc.
- James Beausang
- G01 - MEASURING TESTING
Information Patent Grant
System and method for generating effective layout constraints for a...
- Patent number 6,058,252
- Issue date May 2, 2000
- Synopsys, Inc.
- Mark D. Noll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical scan architecture for design for test applications
- Patent number 5,949,692
- Issue date Sep 7, 1999
- Synopsys, Inc.
- James Beausang
- G01 - MEASURING TESTING
Information Patent Grant
Constraint driven insertion of scan logic for implementing design f...
- Patent number 5,903,466
- Issue date May 11, 1999
- Synopsys, Inc.
- James Beausang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test ready compiler for design for test synthesis
- Patent number 5,831,868
- Issue date Nov 3, 1998
- Synopsys, Inc.
- James Beausang
- G01 - MEASURING TESTING
Information Patent Grant
Test ready compiler for design for test synthesis
- Patent number 5,703,789
- Issue date Dec 30, 1997
- Synopsys, Inc.
- James Beausang
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for performing partial unscan and near full sc...
- Patent number 5,696,771
- Issue date Dec 9, 1997
- Synopsys, Inc.
- James Beausang
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
LOOK-UP BASED BUFFER TREE SYNTHESIS
- Publication number 20140181765
- Publication date Jun 26, 2014
- Synopsys, Inc.
- Sanjay Dhar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELTA-SLACK PROPAGATION FOR CIRCUIT OPTIMIZATION
- Publication number 20130145337
- Publication date Jun 6, 2013
- Synopsys, Inc.
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRESSIVE CIRCUIT EVALUATION FOR CIRCUIT OPTIMIZATION
- Publication number 20130145336
- Publication date Jun 6, 2013
- Synopsys, Inc.
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZONE-BASED AREA RECOVERY IN ELECTRONIC DESIGN AUTOMATION
- Publication number 20110191731
- Publication date Aug 4, 2011
- Synopsys, Inc.
- Robert Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DENSITY-BASED AREA RECOVERY IN ELECTRONIC DESIGN AUTOMATION
- Publication number 20110191738
- Publication date Aug 4, 2011
- Synopsys, Inc.
- Robert Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZONE-BASED OPTIMIZATION FRAMEWORK
- Publication number 20110191740
- Publication date Aug 4, 2011
- Synopsys, Inc.
- Robert Walker
- G06 - COMPUTING CALCULATING COUNTING

Robert Walker

Person

Patents Grantslast 30 patents

Methods for incremental circuit design legalization during physical...

Retiming with fixed power-up states

Retiming with programmable power-up states

Integrated circuit retiming with selective modeling of flip-flop se...

Look-up based buffer tree synthesis

Progressive circuit evaluation for circuit optimization

Delta-slack propagation for circuit optimization

Zone-based area recovery in electronic design automation

Zone-based optimization framework for performing timing and design...

Density-based area recovery in electronic design automation

Electronic design automation system and methods utilizing groups of...

Hierarchical scan architecture for design for test applications

Method and apparatus for performing partial unscan and near full sc...

System and method for generating effective layout constraints for a...

Hierarchical scan architecture for design for test applications

Constraint driven insertion of scan logic for implementing design f...

Test ready compiler for design for test synthesis

Test ready compiler for design for test synthesis

Method and apparatus for performing partial unscan and near full sc...

Patents Applicationslast 30 patents

LOOK-UP BASED BUFFER TREE SYNTHESIS

DELTA-SLACK PROPAGATION FOR CIRCUIT OPTIMIZATION

PROGRESSIVE CIRCUIT EVALUATION FOR CIRCUIT OPTIMIZATION

ZONE-BASED AREA RECOVERY IN ELECTRONIC DESIGN AUTOMATION

DENSITY-BASED AREA RECOVERY IN ELECTRONIC DESIGN AUTOMATION

ZONE-BASED OPTIMIZATION FRAMEWORK