Robert WISER

Person

Santa Cruz, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Chip to chip interconnect beyond sealring boundary
- Patent number 12,308,330
- Issue date May 20, 2025
- Ceremorphic, Inc.
- Robert Wiser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for estimating and compensating for leakage curre...
- Patent number 12,073,903
- Issue date Aug 27, 2024
- Meta Platforms Technologies, LLP
- Umanath Ramachandra Kamath
- G11 - INFORMATION STORAGE
Information Patent Grant
Address dependent wordline timing in asynchronous static random acc...
- Patent number 12,068,024
- Issue date Aug 20, 2024
- Ceremorphic, Inc.
- Jay A. Chesavage
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for scan chain in a memory
- Patent number 11,971,448
- Issue date Apr 30, 2024
- Ceremorphic, Inc.
- Robert F. Wiser
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic adjustment of wordline timing in static random access memory
- Patent number 11,935,587
- Issue date Mar 19, 2024
- Ceremorphic, Inc.
- Robert F. Wiser
- G11 - INFORMATION STORAGE
Information Patent Grant
One transistor memory bitcell with arithmetic capability
- Patent number 11,862,282
- Issue date Jan 2, 2024
- Ceremorphic, Inc.
- Neelam Surana
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan chain for memory with reduced power consumption
- Patent number 11,693,056
- Issue date Jul 4, 2023
- Ceremorphic, Inc.
- Robert F. Wiser
- G01 - MEASURING TESTING
Information Patent Grant
Chip to chip network routing using DC bias and differential signaling
- Patent number 11,689,443
- Issue date Jun 27, 2023
- Ceremorphic, Inc.
- Robert Wiser
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Chip to chip communication routing using header amplitude
- Patent number 11,632,324
- Issue date Apr 18, 2023
- Ceremorphic, Inc.
- Robert Wiser
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Dynamic Adjustment of Word Line Timing in Static Dynamic Random Acc...
- Publication number 20240428850
- Publication date Dec 26, 2024
- Ceremorphic, Inc.
- Jay A. CHESAVAGE
- G11 - INFORMATION STORAGE
Information Patent Application
TIME MULTIPLEXING OF BOOTSTRAP SAMPLE NETWORK
- Publication number 20240313771
- Publication date Sep 19, 2024
- Meta Platforms Technologies, LLC
- Umanath Ramachandra Kamath
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit And System For Reducing Current Leakage
- Publication number 20240283444
- Publication date Aug 22, 2024
- Meta Platforms Technologies, LLC
- Umanath Ramachandra Kamath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method And System For Estimating And Compensating For Leakage Curre...
- Publication number 20240282398
- Publication date Aug 22, 2024
- Meta Platforms Technologies, LLC
- Umanath Ramachandra Kamath
- G11 - INFORMATION STORAGE
Information Patent Application
Dynamic Adjustment of Word Line Timing in Static Random Access Memory
- Publication number 20230352082
- Publication date Nov 2, 2023
- Ceremorphic, Inc.
- Jay A. CHESAVAGE
- G11 - INFORMATION STORAGE
Information Patent Application
Process for Scan Chain in a Memory
- Publication number 20230296672
- Publication date Sep 21, 2023
- Ceremorphic, Inc.
- Robert F. Wiser
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
One Transistor Memory Bitcell with Arithmetic Capability
- Publication number 20230197121
- Publication date Jun 22, 2023
- Ceremorphic, Inc.
- Neelam SURANA
- G11 - INFORMATION STORAGE
Information Patent Application
Dynamic Adjustment of Wordline Timing In Static Random Access Memory
- Publication number 20230197146
- Publication date Jun 22, 2023
- Ceremorphic, Inc.
- Robert F. WISER
- G11 - INFORMATION STORAGE
Information Patent Application
Scan Chain for Memory with Reduced Power Consumption
- Publication number 20230194607
- Publication date Jun 22, 2023
- Ceremorphic, Inc.
- Shakti SINGH
- G01 - MEASURING TESTING
Information Patent Application
Chip to Chip Interconnect Beyond Sealring Boundary
- Publication number 20220415827
- Publication date Dec 29, 2022
- Ceremorphic, Inc.
- Robert Wiser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip to Chip Communication routing using Header Amplitude
- Publication number 20220385566
- Publication date Dec 1, 2022
- Redpine Signals, Inc.
- Robert WISER
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Chip to Chip Network Routing using DC Bias and Differential Signaling
- Publication number 20220385565
- Publication date Dec 1, 2022
- Redpine Signals, Inc.
- Robert WISER
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Robert WISER

Person

Patents Grantslast 30 patents

Chip to chip interconnect beyond sealring boundary

Method and system for estimating and compensating for leakage curre...

Address dependent wordline timing in asynchronous static random acc...

Process for scan chain in a memory

Dynamic adjustment of wordline timing in static random access memory

One transistor memory bitcell with arithmetic capability

Scan chain for memory with reduced power consumption

Chip to chip network routing using DC bias and differential signaling

Chip to chip communication routing using header amplitude

Patents Applicationslast 30 patents

Dynamic Adjustment of Word Line Timing in Static Dynamic Random Acc...

TIME MULTIPLEXING OF BOOTSTRAP SAMPLE NETWORK

Circuit And System For Reducing Current Leakage

Method And System For Estimating And Compensating For Leakage Curre...

Dynamic Adjustment of Word Line Timing in Static Random Access Memory

Process for Scan Chain in a Memory

One Transistor Memory Bitcell with Arithmetic Capability

Dynamic Adjustment of Wordline Timing In Static Random Access Memory

Scan Chain for Memory with Reduced Power Consumption

Chip to Chip Interconnect Beyond Sealring Boundary

Chip to Chip Communication routing using Header Amplitude

Chip to Chip Network Routing using DC Bias and Differential Signaling