Robertus Laurentius van der Valk

Person

Capelle aan den Ijssel, NL

People

Patents Grantslast 30 patents

Information Patent Grant
Method of recovering timing over a granular packet network
- Patent number 7,738,501
- Issue date Jun 15, 2010
- Zarlink Semiconductor, Inc.
- Willem L. Repko
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flexible waveform generator with extended range capability
- Patent number 7,728,634
- Issue date Jun 1, 2010
- Zarlink Semiconductor Inc.
- Johannes Hermanus Aloysius De Rijk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital phase locked loop
- Patent number 7,642,862
- Issue date Jan 5, 2010
- Zarlink Semiconductor Inc.
- Robertus Laurentius van der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Asynchronous phase acquisition unit with dithering
- Patent number 7,619,483
- Issue date Nov 17, 2009
- Zarlink Semiconductor Inc.
- Robertus Laurentius van der Valk
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Fractional digital PLL
- Patent number 7,557,624
- Issue date Jul 7, 2009
- Zarlink Semiconductor Inc.
- Robertus Laurentius van der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method to improve the resolution of time measurements and alignment...
- Patent number 7,385,990
- Issue date Jun 10, 2008
- Zarlink Semiconductor Inc.
- Willem L. Repko
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Alignment of clocks over multiple packet networks
- Patent number 7,376,156
- Issue date May 20, 2008
- Zarlink Semiconductor Inc.
- Willem L. Repko
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase locked loop fast lock method
- Patent number 7,369,002
- Issue date May 6, 2008
- Zarlink Semiconductor, Inc.
- Menno Tjeerd Spijker
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method providing distribution means for reference clocks across pac...
- Patent number 7,356,036
- Issue date Apr 8, 2008
- Zarlink Semiconductor Inc.
- Robertus Laurentius Van Der Valk
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Alignment of clock domains in packet networks
- Patent number 7,315,546
- Issue date Jan 1, 2008
- Zarlink Semiconductor Inc.
- Willem L. Repko
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flexible decimator
- Patent number 7,096,243
- Issue date Aug 22, 2006
- Zarlink Semiconductor Inc.
- Robertus Laurentius Van Der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Analog PLL with switched capacitor resampling filter
- Patent number 7,078,946
- Issue date Jul 18, 2006
- Zarlink Semiconductor Inc.
- Robertus Laurentius van der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed digital counters
- Patent number 6,795,520
- Issue date Sep 21, 2004
- Zarlink Semiconductor Inc.
- Robertus Laurentius Van Der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of stabilizing phase-locked loop
- Patent number 6,784,706
- Issue date Aug 31, 2004
- Zarlink Semiconductor, Inc.
- Robertus Laurentius Van Der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Frequency synthesizer
- Patent number 5,905,388
- Issue date May 18, 1999
- X Integrated Circuits B.V.
- Robertus L. Van Der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
FLEXIBLE WAVEFORM GENERATOR WITH EXTENDED RANGE CAPABILITY
- Publication number 20090184736
- Publication date Jul 23, 2009
- Zarlink Semiconductor Inc.
- Johannes Hermanus Aloysius De Rijk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FRACTIONAL DIGITAL PLL
- Publication number 20080122504
- Publication date May 29, 2008
- Zarlink Semiconductor Inc.
- Robertus Laurentius van der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ASYNCHRONOUS PHASE ACQUISITION UNIT WITH DITHERING
- Publication number 20080116980
- Publication date May 22, 2008
- Zarlink Semiconductor Inc.
- Robertus Laurentius van der Valk
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DIGITAL PHASE LOCKED LOOP
- Publication number 20080116982
- Publication date May 22, 2008
- Zarlink Semiconductor Inc.
- Robertus Laurentius van der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase Locked Loop Fast Lock Method
- Publication number 20070024383
- Publication date Feb 1, 2007
- Zarlink Semiconductor Inc.
- Menno Tjeerd Spijker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method of recovering timing over a granular packet network
- Publication number 20060269029
- Publication date Nov 30, 2006
- Zarlink Semiconductor Inc.
- Willem L. Repko
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method to improve the resolution of time measurements and alignment...
- Publication number 20050053076
- Publication date Mar 10, 2005
- Zarlink Semiconductor Inc.
- Willem L. Repko
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method providing distribution means for reference clocks across pac...
- Publication number 20040264478
- Publication date Dec 30, 2004
- Zarlink Semiconductor Inc.
- Robertus Laurentius Van Der Valk
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Alignment of clock domains in packet networks
- Publication number 20040264477
- Publication date Dec 30, 2004
- Zarlink Semiconductor Inc.
- Willem L. Repko
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Alignment of clocks over multiple packet networks
- Publication number 20040223518
- Publication date Nov 11, 2004
- Zarlink Semiconductor Inc.
- Willem L. Repko
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method of measuring the accuracy of a clock signal
- Publication number 20040153894
- Publication date Aug 5, 2004
- Zarlink Semiconductor Inc.
- Robertus Laurentius van der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Flexible decimator
- Publication number 20030177156
- Publication date Sep 18, 2003
- Zarlink Semiconductor Inc.
- Robertus Laurentius Van Der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
High speed digital counters
- Publication number 20030169841
- Publication date Sep 11, 2003
- Zarlink Semiconductor Inc.
- Robertus Laurentius van der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Analog PLL with switched capacitor resampling filter
- Publication number 20030155950
- Publication date Aug 21, 2003
- Zarlink Semiconductor Inc.
- Robertus Laurentius van der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method of stabilizing phase-locked loop
- Publication number 20030137329
- Publication date Jul 24, 2003
- Zarlink Semiconductor Inc.
- Robertus Laurentius Van Der Valk
- H03 - BASIC ELECTRONIC CIRCUITRY

Robertus Laurentius van der Valk

Person

Patents Grantslast 30 patents

Method of recovering timing over a granular packet network

Flexible waveform generator with extended range capability

Digital phase locked loop

Asynchronous phase acquisition unit with dithering

Fractional digital PLL

Method to improve the resolution of time measurements and alignment...

Alignment of clocks over multiple packet networks

Phase locked loop fast lock method

Method providing distribution means for reference clocks across pac...

Alignment of clock domains in packet networks

Flexible decimator

Analog PLL with switched capacitor resampling filter

High speed digital counters

Method of stabilizing phase-locked loop

Frequency synthesizer

Patents Applicationslast 30 patents

FLEXIBLE WAVEFORM GENERATOR WITH EXTENDED RANGE CAPABILITY

FRACTIONAL DIGITAL PLL

ASYNCHRONOUS PHASE ACQUISITION UNIT WITH DITHERING

DIGITAL PHASE LOCKED LOOP

Phase Locked Loop Fast Lock Method

Method of recovering timing over a granular packet network

Method to improve the resolution of time measurements and alignment...

Method providing distribution means for reference clocks across pac...

Alignment of clock domains in packet networks

Alignment of clocks over multiple packet networks

Method of measuring the accuracy of a clock signal

Flexible decimator

High speed digital counters

Analog PLL with switched capacitor resampling filter

Method of stabilizing phase-locked loop