Roden Topacio

Person

Markham, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Electronic device including a substrate, a structure, and an adhesi...
- Patent number 12,148,715
- Issue date Nov 19, 2024
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package assembly using a passive device as a standoff
- Patent number 11,942,405
- Issue date Mar 26, 2024
- ATI Technologies ULC
- Jianguo Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip with patterned underbump metallization and polym...
- Patent number 11,335,659
- Issue date May 17, 2022
- ATI Technologies ULC
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit product customizations for identification code v...
- Patent number 11,315,883
- Issue date Apr 26, 2022
- Advanced Micro Devices, Inc.
- Suming Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit board with constrained solder interconnect pads
- Patent number 10,431,533
- Issue date Oct 1, 2019
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect etch with polymer layer edge protection
- Patent number 10,403,589
- Issue date Sep 3, 2019
- ATI Technologies ULC
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect etch with polymer layer edge protection
- Patent number 9,728,518
- Issue date Aug 8, 2017
- ATI Technologies ULC
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip with patterned underbump metallization and polym...
- Patent number 9,576,923
- Issue date Feb 21, 2017
- ATI Technologies ULC
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of fabricating semiconductor chip solder structures
- Patent number 9,318,457
- Issue date Apr 19, 2016
- ATI Technologies ULC
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermal management circuit board for stacked semiconductor chip device
- Patent number 9,209,106
- Issue date Dec 8, 2015
- ATI Technologies ULC
- Xiao Ling Shi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods of fabricating semiconductor chip solder structures
- Patent number 9,142,520
- Issue date Sep 22, 2015
- ATI Technologies ULC
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Routing layer for mitigating stress in a semiconductor die
- Patent number 9,059,159
- Issue date Jun 16, 2015
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Routing layer for mitigating stress in a semiconductor die
- Patent number 9,035,471
- Issue date May 19, 2015
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die substrate with reinforcement structure
- Patent number 8,927,344
- Issue date Jan 6, 2015
- ATI Technologies ULC
- Roden Topacio
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit package strip with stiffener
- Patent number 8,847,383
- Issue date Sep 30, 2014
- ATI Technologies ULC
- Neil R. McLellan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder mask with anchor structures
- Patent number 8,772,083
- Issue date Jul 8, 2014
- ATI Technologies ULC
- Andrew K W Leung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Routing layer for mitigating stress in a semiconductor die
- Patent number 8,664,777
- Issue date Mar 4, 2014
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a semiconductor chip with supportive terminal...
- Patent number 8,647,974
- Issue date Feb 11, 2014
- ATI Technologies ULC
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Routing layer for mitigating stress in a semiconductor die
- Patent number 8,642,463
- Issue date Feb 4, 2014
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Face-to-face (F2F) hybrid structure for an integrated circuit
- Patent number 8,637,983
- Issue date Jan 28, 2014
- ATI Technologies ULC
- Liane Martinez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor chip with underfill anchors
- Patent number 8,633,599
- Issue date Jan 21, 2014
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming semiconductor chip underfill anchors
- Patent number 8,389,340
- Issue date Mar 5, 2013
- ATI Technologies ULC
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip bump connection apparatus and method
- Patent number 8,378,471
- Issue date Feb 19, 2013
- ATI Technologies ULC
- Roden R. Topacio
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Die substrate with reinforcement structure
- Patent number 8,313,984
- Issue date Nov 20, 2012
- ATI Technologies ULC
- Roden Topacio
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of manufacturing substrates having asymmetric buildup layers
- Patent number 8,298,945
- Issue date Oct 30, 2012
- ATI Technologies ULC
- Andrew Leung
- B32 - LAYERED PRODUCTS
Information Patent Grant
Routing layer for mitigating stress in a semiconductor die
- Patent number 8,299,632
- Issue date Oct 30, 2012
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductor bump method and apparatus
- Patent number 8,294,266
- Issue date Oct 23, 2012
- Advanced Micro Devices, Inc.
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Routing layer for mitigating stress in a semiconductor die
- Patent number 8,227,926
- Issue date Jul 24, 2012
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated package circuit with stiffener
- Patent number 8,120,170
- Issue date Feb 21, 2012
- ATI Technologies ULC
- Neil R. McLellan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming semiconductor chip underfill anchors
- Patent number 8,058,108
- Issue date Nov 15, 2011
- ATI Technologies ULC
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LID ASSEMBLY FOR A CHIP PACKAGE
- Publication number 20240332098
- Publication date Oct 3, 2024
- ADVANCED MICRO DEVICES, INC.
- Suming HU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR ASSEMBLY INCLUDING MULTIPLE SOLDER MASKS
- Publication number 20240038703
- Publication date Feb 1, 2024
- ATI Technologies ULC
- JIANGUO LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE INCLUDING A SUBSTRATE, A STRUCTURE, AND AN ADHESI...
- Publication number 20230187379
- Publication date Jun 15, 2023
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE ASSEMBLY USING A PASSIVE DEVICE AS A STANDOFF
- Publication number 20230154834
- Publication date May 18, 2023
- ATI Technologies ULC
- JIANGUO LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PRODUCT CUSTOMIZATIONS FOR IDENTIFICATION CODE V...
- Publication number 20210143104
- Publication date May 13, 2021
- ADVANCED MICRO DEVICES, INC.
- Suming Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT ETCH WITH POLYMER LAYER EDGE PROTECTION
- Publication number 20170301638
- Publication date Oct 19, 2017
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION AND POLYM...
- Publication number 20170110428
- Publication date Apr 20, 2017
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT BOARD WITH CONSTRAINED SOLDER INTERCONNECT PADS
- Publication number 20160126171
- Publication date May 5, 2016
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FABRICATING SEMICONDUCTOR CHIP SOLDER STRUCTURES
- Publication number 20150340334
- Publication date Nov 26, 2015
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION AND POLYM...
- Publication number 20150279794
- Publication date Oct 1, 2015
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT ETCH WITH POLYMER LAYER EDGE PROTECTION
- Publication number 20150279728
- Publication date Oct 1, 2015
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE
- Publication number 20140167261
- Publication date Jun 19, 2014
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE
- Publication number 20140110837
- Publication date Apr 24, 2014
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMAL MANAGEMENT CIRCUIT BOARD FOR STACKED SEMICONDUCTOR CHIP D...
- Publication number 20130343000
- Publication date Dec 26, 2013
- Xiao Ling Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP DEVICE WITH FRAGMENTED SOLDER STRUCTURE PADS
- Publication number 20130256871
- Publication date Oct 3, 2013
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP WITH UNDERFILL ANCHORS
- Publication number 20130154122
- Publication date Jun 20, 2013
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HEATSINK INTERPOSER
- Publication number 20130147026
- Publication date Jun 13, 2013
- ATI Technologies ULC
- Roden R. TOPACIO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR SUBSTRATE WITH MOLDED SUPPORT LAYER
- Publication number 20130113084
- Publication date May 9, 2013
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE SUBSTRATE WITH REINFORCEMENT STRUCTURE
- Publication number 20130069250
- Publication date Mar 21, 2013
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLDER MASK WITH ANCHOR STRUCTURES
- Publication number 20130062786
- Publication date Mar 14, 2013
- Andrew KW Leung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FABRICATING SEMICONDUCTOR CHIP SOLDER STRUCTURES
- Publication number 20130049190
- Publication date Feb 28, 2013
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE
- Publication number 20130032941
- Publication date Feb 7, 2013
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP WITH DUAL POLYMER FILM INTERCONNECT STRUCTURES
- Publication number 20120326299
- Publication date Dec 27, 2012
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE
- Publication number 20120270388
- Publication date Oct 25, 2012
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION
- Publication number 20120261812
- Publication date Oct 18, 2012
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR CHIP WITH SUPPORTIVE TERMINAL PAD
- Publication number 20120241985
- Publication date Sep 27, 2012
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED PACKAGE CIRCUIT WITH STIFFENER
- Publication number 20120127689
- Publication date May 24, 2012
- ATI Technologies ULC
- Neil R. McLellan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING SEMICONDUCTOR CHIP UNDERFILL ANCHORS
- Publication number 20120012987
- Publication date Jan 19, 2012
- Roden R. Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE
- Publication number 20110254154
- Publication date Oct 20, 2011
- ATI Technologies ULC
- Roden Topacio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS
- Publication number 20110225813
- Publication date Sep 22, 2011
- ATI Technologies ULC
- Andrew Leung
- B32 - LAYERED PRODUCTS

Roden Topacio

Person

Patents Grantslast 30 patents

Electronic device including a substrate, a structure, and an adhesi...

Semiconductor package assembly using a passive device as a standoff

Semiconductor chip with patterned underbump metallization and polym...

Integrated circuit product customizations for identification code v...

Circuit board with constrained solder interconnect pads

Interconnect etch with polymer layer edge protection

Interconnect etch with polymer layer edge protection

Semiconductor chip with patterned underbump metallization and polym...

Methods of fabricating semiconductor chip solder structures

Thermal management circuit board for stacked semiconductor chip device

Methods of fabricating semiconductor chip solder structures

Routing layer for mitigating stress in a semiconductor die

Routing layer for mitigating stress in a semiconductor die

Die substrate with reinforcement structure

Integrated circuit package strip with stiffener

Solder mask with anchor structures

Routing layer for mitigating stress in a semiconductor die

Method of fabricating a semiconductor chip with supportive terminal...

Routing layer for mitigating stress in a semiconductor die

Face-to-face (F2F) hybrid structure for an integrated circuit

Semiconductor chip with underfill anchors

Methods of forming semiconductor chip underfill anchors

Semiconductor chip bump connection apparatus and method

Die substrate with reinforcement structure

Method of manufacturing substrates having asymmetric buildup layers

Routing layer for mitigating stress in a semiconductor die

Conductor bump method and apparatus

Routing layer for mitigating stress in a semiconductor die

Integrated package circuit with stiffener

Methods of forming semiconductor chip underfill anchors

Patents Applicationslast 30 patents

LID ASSEMBLY FOR A CHIP PACKAGE

SEMICONDUCTOR ASSEMBLY INCLUDING MULTIPLE SOLDER MASKS

ELECTRONIC DEVICE INCLUDING A SUBSTRATE, A STRUCTURE, AND AN ADHESI...

SEMICONDUCTOR PACKAGE ASSEMBLY USING A PASSIVE DEVICE AS A STANDOFF

INTEGRATED CIRCUIT PRODUCT CUSTOMIZATIONS FOR IDENTIFICATION CODE V...

INTERCONNECT ETCH WITH POLYMER LAYER EDGE PROTECTION

SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION AND POLYM...

CIRCUIT BOARD WITH CONSTRAINED SOLDER INTERCONNECT PADS

METHODS OF FABRICATING SEMICONDUCTOR CHIP SOLDER STRUCTURES

SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION AND POLYM...

INTERCONNECT ETCH WITH POLYMER LAYER EDGE PROTECTION

ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE

ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE

THERMAL MANAGEMENT CIRCUIT BOARD FOR STACKED SEMICONDUCTOR CHIP D...

SEMICONDUCTOR CHIP DEVICE WITH FRAGMENTED SOLDER STRUCTURE PADS

SEMICONDUCTOR CHIP WITH UNDERFILL ANCHORS

HEATSINK INTERPOSER

SEMICONDUCTOR SUBSTRATE WITH MOLDED SUPPORT LAYER

DIE SUBSTRATE WITH REINFORCEMENT STRUCTURE

SOLDER MASK WITH ANCHOR STRUCTURES

METHODS OF FABRICATING SEMICONDUCTOR CHIP SOLDER STRUCTURES

ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE

SEMICONDUCTOR CHIP WITH DUAL POLYMER FILM INTERCONNECT STRUCTURES

ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE

SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION

SEMICONDUCTOR CHIP WITH SUPPORTIVE TERMINAL PAD

INTEGRATED PACKAGE CIRCUIT WITH STIFFENER

METHODS OF FORMING SEMICONDUCTOR CHIP UNDERFILL ANCHORS

ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE

METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS