Rodrigo Alvarez-Icaza Rivera

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hardware architecture for simulating a neural network of neurons
- Patent number 11,341,401
- Issue date May 24, 2022
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Yield tolerance in a neurosynaptic system
- Patent number 11,184,221
- Issue date Nov 23, 2021
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event-based neural network with hierarchical addressing for routing...
- Patent number 11,049,001
- Issue date Jun 29, 2021
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Peripheral device interconnections for neurosynaptic systems
- Patent number 10,984,307
- Issue date Apr 20, 2021
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Globally asynchronous and locally synchronous (GALS) neuromorphic n...
- Patent number 10,839,287
- Issue date Nov 17, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scaling multi-core neurosynaptic networks across chip boundaries
- Patent number 10,785,745
- Issue date Sep 22, 2020
- International Business Machines Corporation
- Rodrigo Alvarez Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Converting digital numeric data to spike event data
- Patent number 10,769,519
- Issue date Sep 8, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Converting spike event data to digital numeric data
- Patent number 10,755,165
- Issue date Aug 25, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplexing physical neurons to optimize power and area
- Patent number 10,713,561
- Issue date Jul 14, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Utilizing a distributed and parallel set of neurosynaptic core circ...
- Patent number 10,650,301
- Issue date May 12, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Yield tolerance in a neurosynaptic system
- Patent number 10,454,759
- Issue date Oct 22, 2019
- International Business Machines Corporation
- Rodrigo Alvarez Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Peripheral device interconnections for neurosynaptic systems
- Patent number 10,410,109
- Issue date Sep 10, 2019
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware architecture for simulating a neural network of neurons
- Patent number 10,282,658
- Issue date May 7, 2019
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping neural dynamics of a neural model on to a coarsely grained...
- Patent number 10,204,118
- Issue date Feb 12, 2019
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Faulty core recovery mechanisms for a three-dimensional network on...
- Patent number 10,176,063
- Issue date Jan 8, 2019
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neuromorphic network comprising asynchronous routers and synchronou...
- Patent number 10,169,700
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event-based neural network with hierarchical addressing for routing...
- Patent number 10,102,474
- Issue date Oct 16, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Yield tolerance in a neurosynaptic system
- Patent number 9,992,057
- Issue date Jun 5, 2018
- International Business Machines Corporation
- Rodrigo Alvarez Icaza Rivera
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interconnect circuits at three dimensional (3-D) bonding interfaces...
- Patent number 9,940,302
- Issue date Apr 10, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scaling multi-core neurosynaptic networks across chip boundaries
- Patent number 9,924,490
- Issue date Mar 20, 2018
- International Business Machines Corporation
- Rodrigo Alvarez Icaza Rivera
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Converting spike event data to digital numeric data
- Patent number 9,886,662
- Issue date Feb 6, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Converting digital numeric data to spike event data
- Patent number 9,881,252
- Issue date Jan 30, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Consolidating multiple neurosynaptic core circuits into one reconfi...
- Patent number 9,852,006
- Issue date Dec 26, 2017
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Initializing and testing integrated circuits with selectable scan c...
- Patent number 9,797,946
- Issue date Oct 24, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G01 - MEASURING TESTING
Information Patent Grant
Array of processor core circuits with reversible tiers
- Patent number 9,792,251
- Issue date Oct 17, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-timed, event-driven neurosynaptic core controller
- Patent number 9,747,545
- Issue date Aug 29, 2017
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Array of processor core circuits with reversible tiers
- Patent number 9,588,937
- Issue date Mar 7, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Globally asynchronous and locally synchronous (GALS) neuromorphic n...
- Patent number 9,563,841
- Issue date Feb 7, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware architecture for simulating a neural network of neurons
- Patent number 9,466,022
- Issue date Oct 11, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping neural dynamics of a neural model on to a coarsely grained...
- Patent number 9,424,284
- Issue date Aug 23, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EVENT-BASED NEURAL NETWORK WITH HIERARCHICAL ADDRESSING FOR ROUTING...
- Publication number 20210166107
- Publication date Jun 3, 2021
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBALLY ASYNCHRONOUS AND LOCALLY SYNCHRONOUS (GALS) NEUROMORPHIC N...
- Publication number 20200364535
- Publication date Nov 19, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
YIELD TOLERANCE IN A NEUROSYNAPTIC SYSTEM
- Publication number 20190372831
- Publication date Dec 5, 2019
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERIPHERAL DEVICE INTERCONNECTIONS FOR NEUROSYNAPTIC SYSTEMS
- Publication number 20190294950
- Publication date Sep 26, 2019
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ARCHITECTURE FOR SIMULATING A NEURAL NETWORK OF NEURONS
- Publication number 20190197394
- Publication date Jun 27, 2019
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
YIELD TOLERANCE IN A NEUROSYNAPTIC SYSTEM
- Publication number 20180287862
- Publication date Oct 4, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...
- Publication number 20180189233
- Publication date Jul 5, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAPPING NEURAL DYNAMICS OF A NEURAL MODEL ON TO A COARSELY GRAINED...
- Publication number 20180113885
- Publication date Apr 26, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALING MULTI-CORE NEUROSYNAPTIC NETWORKS ACROSS CHIP BOUNDARIES
- Publication number 20180103448
- Publication date Apr 12, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVERTING SPIKE EVENT DATA TO DIGITAL NUMERIC DATA
- Publication number 20180082174
- Publication date Mar 22, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVERTING DIGITAL NUMERIC DATA TO SPIKE EVENT DATA
- Publication number 20180082173
- Publication date Mar 22, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INITIALIZING AND TESTING INTEGRATED CIRCUITS WITH SELECTABLE SCAN C...
- Publication number 20170199241
- Publication date Jul 13, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G01 - MEASURING TESTING
Information Patent Application
ARRAY OF PROCESSOR CORE CIRCUITS WITH REVERSIBLE TIERS
- Publication number 20170124024
- Publication date May 4, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBALLY ASYNCHRONOUS AND LOCALLY SYNCHRONOUS (GALS) NEUROMORPHIC N...
- Publication number 20170076197
- Publication date Mar 16, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ARCHITECTURE FOR SIMULATING A NEURAL NETWORK OF NEURONS
- Publication number 20160358066
- Publication date Dec 8, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
YIELD TOLERANCE IN A NEUROSYNAPTIC SYSTEM
- Publication number 20160323137
- Publication date Nov 3, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVENT-BASED NEURAL NETWORK WITH HIERARCHICAL ADDRESSING
- Publication number 20160321539
- Publication date Nov 3, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSOLIDATING MULTIPLE NEUROSYNAPTIC CORE CIRCUITS INTO ONE RECONFI...
- Publication number 20160321537
- Publication date Nov 3, 2016
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON...
- Publication number 20160239393
- Publication date Aug 18, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT CIRCUITS AT THREE DIMENSIONAL (3-D) BONDING INTERFACES...
- Publication number 20160232128
- Publication date Aug 11, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALING MULTI-CORE NEUROSYNAPTIC NETWORKS ACROSS CHIP BOUNDARIES
- Publication number 20160224889
- Publication date Aug 4, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON...
- Publication number 20160154717
- Publication date Jun 2, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...
- Publication number 20160148901
- Publication date May 26, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-TIMED, EVENT-DRIVEN NEUROSYNAPTIC CORE CONTROLLER
- Publication number 20160086077
- Publication date Mar 24, 2016
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVERTING DIGITAL NUMERIC DATA TO SPIKE EVENT DATA
- Publication number 20160086075
- Publication date Mar 24, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVERTING SPIKE EVENT DATA TO DIGITAL NUMERIC DATA
- Publication number 20160086076
- Publication date Mar 24, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERIPHERAL DEVICE INTERCONNECTIONS FOR NEUROSYNAPTIC SYSTEMS
- Publication number 20160055408
- Publication date Feb 25, 2016
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ARCHITECTURE FOR SIMULATING A NEURAL NETWORK OF NEURONS
- Publication number 20160034808
- Publication date Feb 4, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLEXING PHYSICAL NEURONS TO OPTIMIZE POWER AND AREA
- Publication number 20150379393
- Publication date Dec 31, 2015
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEUROMORPHIC HARDWARE FOR NEURONAL COMPUTATION AND NON-NEURONAL COM...
- Publication number 20150324684
- Publication date Nov 12, 2015
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING

Rodrigo Alvarez-Icaza Rivera

Person

Patents Grantslast 30 patents

Hardware architecture for simulating a neural network of neurons

Yield tolerance in a neurosynaptic system

Event-based neural network with hierarchical addressing for routing...

Peripheral device interconnections for neurosynaptic systems

Globally asynchronous and locally synchronous (GALS) neuromorphic n...

Scaling multi-core neurosynaptic networks across chip boundaries

Converting digital numeric data to spike event data

Converting spike event data to digital numeric data

Multiplexing physical neurons to optimize power and area

Utilizing a distributed and parallel set of neurosynaptic core circ...

Yield tolerance in a neurosynaptic system

Peripheral device interconnections for neurosynaptic systems

Hardware architecture for simulating a neural network of neurons

Mapping neural dynamics of a neural model on to a coarsely grained...

Faulty core recovery mechanisms for a three-dimensional network on...

Neuromorphic network comprising asynchronous routers and synchronou...

Event-based neural network with hierarchical addressing for routing...

Yield tolerance in a neurosynaptic system

Interconnect circuits at three dimensional (3-D) bonding interfaces...

Scaling multi-core neurosynaptic networks across chip boundaries

Converting spike event data to digital numeric data

Converting digital numeric data to spike event data

Consolidating multiple neurosynaptic core circuits into one reconfi...

Initializing and testing integrated circuits with selectable scan c...

Array of processor core circuits with reversible tiers

Self-timed, event-driven neurosynaptic core controller

Array of processor core circuits with reversible tiers

Globally asynchronous and locally synchronous (GALS) neuromorphic n...

Hardware architecture for simulating a neural network of neurons

Mapping neural dynamics of a neural model on to a coarsely grained...

Patents Applicationslast 30 patents

EVENT-BASED NEURAL NETWORK WITH HIERARCHICAL ADDRESSING FOR ROUTING...

GLOBALLY ASYNCHRONOUS AND LOCALLY SYNCHRONOUS (GALS) NEUROMORPHIC N...

YIELD TOLERANCE IN A NEUROSYNAPTIC SYSTEM

PERIPHERAL DEVICE INTERCONNECTIONS FOR NEUROSYNAPTIC SYSTEMS

HARDWARE ARCHITECTURE FOR SIMULATING A NEURAL NETWORK OF NEURONS

YIELD TOLERANCE IN A NEUROSYNAPTIC SYSTEM

INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...

MAPPING NEURAL DYNAMICS OF A NEURAL MODEL ON TO A COARSELY GRAINED...

SCALING MULTI-CORE NEUROSYNAPTIC NETWORKS ACROSS CHIP BOUNDARIES

CONVERTING SPIKE EVENT DATA TO DIGITAL NUMERIC DATA

CONVERTING DIGITAL NUMERIC DATA TO SPIKE EVENT DATA

INITIALIZING AND TESTING INTEGRATED CIRCUITS WITH SELECTABLE SCAN C...

ARRAY OF PROCESSOR CORE CIRCUITS WITH REVERSIBLE TIERS

GLOBALLY ASYNCHRONOUS AND LOCALLY SYNCHRONOUS (GALS) NEUROMORPHIC N...

HARDWARE ARCHITECTURE FOR SIMULATING A NEURAL NETWORK OF NEURONS

YIELD TOLERANCE IN A NEUROSYNAPTIC SYSTEM

EVENT-BASED NEURAL NETWORK WITH HIERARCHICAL ADDRESSING

CONSOLIDATING MULTIPLE NEUROSYNAPTIC CORE CIRCUITS INTO ONE RECONFI...

FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON...

INTERCONNECT CIRCUITS AT THREE DIMENSIONAL (3-D) BONDING INTERFACES...

SCALING MULTI-CORE NEUROSYNAPTIC NETWORKS ACROSS CHIP BOUNDARIES

FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON...

INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...

SELF-TIMED, EVENT-DRIVEN NEUROSYNAPTIC CORE CONTROLLER

CONVERTING DIGITAL NUMERIC DATA TO SPIKE EVENT DATA

CONVERTING SPIKE EVENT DATA TO DIGITAL NUMERIC DATA

PERIPHERAL DEVICE INTERCONNECTIONS FOR NEUROSYNAPTIC SYSTEMS

HARDWARE ARCHITECTURE FOR SIMULATING A NEURAL NETWORK OF NEURONS

MULTIPLEXING PHYSICAL NEURONS TO OPTIMIZE POWER AND AREA

NEUROMORPHIC HARDWARE FOR NEURONAL COMPUTATION AND NON-NEURONAL COM...