Roger Espasa

Person

Barcelona, ES

People

Patents Grantslast 30 patents

Information Patent Grant
Bit shuffle processors, methods, systems, and instructions
- Patent number 10,713,044
- Issue date Jul 14, 2020
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for page sizing extension
- Patent number 10,445,244
- Issue date Oct 15, 2019
- Intel Corporation
- Edward Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing a vector permute with an index...
- Patent number 10,445,092
- Issue date Oct 15, 2019
- Intel Corporation
- Jesus Corbal San Adrian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for page sizing extension
- Patent number 10,445,245
- Issue date Oct 15, 2019
- Intel Corporation
- Edward Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing a vector bit shuffle
- Patent number 10,296,489
- Issue date May 21, 2019
- Intel Corporation
- Elmoustapha Ould-Ahmed-Vall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing a vector bit gather
- Patent number 10,296,334
- Issue date May 21, 2019
- Intel Corporation
- Elmoustapha Ould-Ahmed-Vall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for page sizing extension
- Patent number 9,934,155
- Issue date Apr 3, 2018
- Intel Corporation
- Edward Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three source operand floating-point addition instruction with opera...
- Patent number 9,785,433
- Issue date Oct 10, 2017
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Super multiply add (super madd) instruction
- Patent number 9,733,935
- Issue date Aug 15, 2017
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Consecutive bit error detection and correction
- Patent number 9,654,143
- Issue date May 16, 2017
- Intel Corporation
- Guillem Sole
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Indicating a length of an instruction of a variable length instruct...
- Patent number 9,606,931
- Issue date Mar 28, 2017
- Intel Corporation
- Santiago Galan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for setting a vector mask
- Patent number 9,436,468
- Issue date Sep 6, 2016
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for page sizing extension
- Patent number 9,244,855
- Issue date Jan 26, 2016
- Intel Corporation
- Ed Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing vector memory operations
- Patent number 8,707,012
- Issue date Apr 22, 2014
- Intel Corporation
- Roger Espasa
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Adaptively handling remote atomic execution based upon contention p...
- Patent number 8,533,436
- Issue date Sep 10, 2013
- Intel Corporation
- Joshua B. Fryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing vector memory operations
- Patent number 8,316,216
- Issue date Nov 20, 2012
- Intel Corporation
- Roger Espasa
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Implementing vector memory operations
- Patent number 7,627,735
- Issue date Dec 1, 2009
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION
- Publication number 20210374069
- Publication date Dec 2, 2021
- Intel Corporation
- Edward Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
- Publication number 20210132950
- Publication date May 6, 2021
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION
- Publication number 20200242046
- Publication date Jul 30, 2020
- Intel Corporation
- Edward Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX...
- Publication number 20200097290
- Publication date Mar 26, 2020
- Intel Corporation
- JESUS CORBAL SAN ADRIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR VECTOR HORIZONTAL LOGICAL INSTRUCTION
- Publication number 20190138303
- Publication date May 9, 2019
- Intel Corporation
- Elmoustapha OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE SOURCE OPERAND FLOATING-POINT ADDITION INSTRUCTION WITH OPERA...
- Publication number 20180032332
- Publication date Feb 1, 2018
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT GROUP INTERLEAVE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
- Publication number 20170308383
- Publication date Oct 26, 2017
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
- Publication number 20170286112
- Publication date Oct 5, 2017
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION
- Publication number 20170199825
- Publication date Jul 13, 2017
- Edward Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION
- Publication number 20170192904
- Publication date Jul 6, 2017
- Edward Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR VECTOR HORIZONTAL LOGICAL INSTRUCTION
- Publication number 20160283242
- Publication date Sep 29, 2016
- Intel Corporation
- Elmoustapha OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR COMPRESSING A MASK VALUE
- Publication number 20160188333
- Publication date Jun 30, 2016
- Intel Coporation
- ELMOUSTAPHA OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT GATHER
- Publication number 20160188335
- Publication date Jun 30, 2016
- Intel Corporation
- ELMOUSTAPHA OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR FUSED MULTIPLY-MULTIPLY INSTRUCTIONS
- Publication number 20160188327
- Publication date Jun 30, 2016
- Elmoustapha OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR FUSED ADD-ADD INSTRUCTIONS
- Publication number 20160188341
- Publication date Jun 30, 2016
- Elmoustapha OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX...
- Publication number 20160188530
- Publication date Jun 30, 2016
- Intel Corporation
- JESUS CORBAL SAN ADRIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT SHUFFLE
- Publication number 20160188532
- Publication date Jun 30, 2016
- Intel Corporation
- ELMOUSTAPHA OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR VECTOR BROADCAST AND XORAND LOGICAL INSTRU...
- Publication number 20160179523
- Publication date Jun 23, 2016
- Intel Corporation
- Elmoustapha OULD-AHMED-VALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSECUTIVE BIT ERROR DETECTION AND CORRECTION
- Publication number 20150370636
- Publication date Dec 24, 2015
- Guillem Sole
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE SOURCE OPERAND FLOATING POINT ADDITION PROCESSORS, METHODS, S...
- Publication number 20150286482
- Publication date Oct 8, 2015
- Intel Corporation
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING A PLURALITY OF MULTIPLICATION O...
- Publication number 20150277904
- Publication date Oct 1, 2015
- ROGER ESPASA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPER MULTIPLY ADD (SUPER MADD) INSTRUCTION
- Publication number 20140052968
- Publication date Feb 20, 2014
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INDICATING A LENGTH OF AN INSTRUCTION OF A VARIABLE LENGTH INSTRUCT...
- Publication number 20130262771
- Publication date Oct 3, 2013
- Santiago Galan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION
- Publication number 20130117531
- Publication date May 9, 2013
- Edward Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementing Vector Memory Operations
- Publication number 20130036268
- Publication date Feb 7, 2013
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptively Handling Remote Atomic Execution
- Publication number 20100332801
- Publication date Dec 30, 2010
- Joshua B. Fryman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementing Vector Memory Operations
- Publication number 20100042779
- Publication date Feb 18, 2010
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION
- Publication number 20090172344
- Publication date Jul 2, 2009
- Ed Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique for setting a vector mask
- Publication number 20070118720
- Publication date May 24, 2007
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementing vector memory operations
- Publication number 20070094477
- Publication date Apr 26, 2007
- Roger Espasa
- G06 - COMPUTING CALCULATING COUNTING

Roger Espasa

Person

Patents Grantslast 30 patents

Bit shuffle processors, methods, systems, and instructions

Method, system, and apparatus for page sizing extension

Method and apparatus for performing a vector permute with an index...

Method, system, and apparatus for page sizing extension

Method and apparatus for performing a vector bit shuffle

Method and apparatus for performing a vector bit gather

Method, system, and apparatus for page sizing extension

Three source operand floating-point addition instruction with opera...

Super multiply add (super madd) instruction

Consecutive bit error detection and correction

Indicating a length of an instruction of a variable length instruct...

Technique for setting a vector mask

Method, system, and apparatus for page sizing extension

Implementing vector memory operations

Adaptively handling remote atomic execution based upon contention p...

Implementing vector memory operations

Implementing vector memory operations

Patents Applicationslast 30 patents

METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION

BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION

METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX...

APPARATUS AND METHOD FOR VECTOR HORIZONTAL LOGICAL INSTRUCTION

THREE SOURCE OPERAND FLOATING-POINT ADDITION INSTRUCTION WITH OPERA...

BIT GROUP INTERLEAVE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

BIT SHUFFLE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION

METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION

APPARATUS AND METHOD FOR VECTOR HORIZONTAL LOGICAL INSTRUCTION

METHOD AND APPARATUS FOR COMPRESSING A MASK VALUE

METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT GATHER

APPARATUS AND METHOD FOR FUSED MULTIPLY-MULTIPLY INSTRUCTIONS

APPARATUS AND METHOD FOR FUSED ADD-ADD INSTRUCTIONS

METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX...

METHOD AND APPARATUS FOR PERFORMING A VECTOR BIT SHUFFLE

APPARATUS AND METHOD FOR VECTOR BROADCAST AND XORAND LOGICAL INSTRU...

CONSECUTIVE BIT ERROR DETECTION AND CORRECTION

THREE SOURCE OPERAND FLOATING POINT ADDITION PROCESSORS, METHODS, S...

METHOD AND APPARATUS FOR PERFORMING A PLURALITY OF MULTIPLICATION O...

SUPER MULTIPLY ADD (SUPER MADD) INSTRUCTION

INDICATING A LENGTH OF AN INSTRUCTION OF A VARIABLE LENGTH INSTRUCT...

METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION

Implementing Vector Memory Operations

Adaptively Handling Remote Atomic Execution

Implementing Vector Memory Operations

METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION

Technique for setting a vector mask

Implementing vector memory operations