Rohit Bhadana

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Faridabad, IN

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Patents Grantslast 30 patents

Information Patent Grant
Circuit design simulation and clock event reduction
- Patent number 12,086,521
- Issue date Sep 10, 2024
- Xilinx, Inc.
- Tharun Kumar Ksheerasagar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data traffic injection for simulation of circuit designs
- Patent number 11,630,935
- Issue date Apr 18, 2023
- Xilinx, Inc.
- Amit Kasat
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DATA TRAFFIC INJECTION FOR SIMULATION OF CIRCUIT DESIGNS
- Publication number 20230113197
- Publication date Apr 13, 2023
- Xilinx, Inc.
- Amit Kasat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT DESIGN SIMULATION AND CLOCK EVENT REDUCTION
- Publication number 20230114858
- Publication date Apr 13, 2023
- Xilinx, Inc.
- Tharun Kumar Ksheerasagar
- G06 - COMPUTING CALCULATING COUNTING