Rohit Bhatia

Person

Ft. Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Balanced P-LRU tree for a “multiple of 3” number of ways cache
- Patent number 9,348,766
- Issue date May 24, 2016
- Intel Corporation
- Adi Basel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent page table walker control for TLB miss handling
- Patent number 9,069,690
- Issue date Jun 30, 2015
- Intel Corporation
- Gur Hildesheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for reducing step loads of processors
- Patent number 8,886,979
- Issue date Nov 11, 2014
- Intel Corporation
- Kevin Safford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for reducing step loads of processors
- Patent number 8,479,029
- Issue date Jul 2, 2013
- Intel Corporation
- Kevin Safford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mitigating context switch cache miss penalty
- Patent number 8,219,780
- Issue date Jul 10, 2012
- Hewlett-Packard Development Company, L.P.
- James R. Callister
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatuses for reducing step loads of processors
- Patent number 7,992,017
- Issue date Aug 2, 2011
- Intel Corporation
- Kevin Safford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system resource access control
- Patent number 7,930,539
- Issue date Apr 19, 2011
- Hewlett-Packard Development Company, L.P.
- Donald C. Soltis, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods of sharing processing resources in a multi-thre...
- Patent number 7,856,636
- Issue date Dec 21, 2010
- Hewlett-Packard Development Company, L.P.
- Rohit Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor-architecture for facilitating a virtual machine monitor
- Patent number 7,421,689
- Issue date Sep 2, 2008
- Hewlett-Packard Development Company, L.P.
- Jonathan K. Ross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for responding to TLB misses
- Patent number 7,409,524
- Issue date Aug 5, 2008
- Hewlett-Packard Development Company, L.P.
- Kevin Safford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using thread urgency in determining switch events in a temporal mul...
- Patent number 7,213,134
- Issue date May 1, 2007
- Hewlett-Packard Development Company, L.P.
- Donald C. Soltis, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for preserving pipeline data during a pipeline...
- Patent number 6,910,122
- Issue date Jun 21, 2005
- Hewlett-Packard Development Company, L.P.
- Stephen L. Bass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for resetting and initializing a fully associativ...
- Patent number 6,823,434
- Issue date Nov 23, 2004
- Hewlett-Packard Development Company, L.P.
- David P Hannum
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for efficiently generating, storing, and consu...
- Patent number 6,807,625
- Issue date Oct 19, 2004
- Hewlett-Packard Development Company, L.P.
- Patrick Knebel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for efficiently updating a fully associative array
- Patent number 6,775,752
- Issue date Aug 10, 2004
- Hewlett-Packard Development Company, L.P.
- Rohit Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for conditionally flushing a pipeline upon a f...
- Patent number 6,745,322
- Issue date Jun 1, 2004
- Hewlett-Packard Development Company, L.P.
- Russell C Brockmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for data forwarding
- Patent number 6,707,831
- Issue date Mar 16, 2004
- Hewlett-Packard Development Company, L.P.
- Eric S Fetzer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for resteering failing speculation check instr...
- Patent number 6,636,960
- Issue date Oct 21, 2003
- Hewlett-Packard Development Company, L.P.
- James Douglas Gibson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for finding and validating the most recent advanc...
- Patent number 6,618,803
- Issue date Sep 9, 2003
- Hewlett-Packard Development Company, L.P.
- David P Hannum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local stall/hazard detect in superscalar, pipelined microprocessor
- Patent number 6,591,360
- Issue date Jul 8, 2003
- Hewlett-Packard Development Company
- Donald C. Soltis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local stall/hazard detect in superscalar, pipelined microprocessor...
- Patent number 6,587,940
- Issue date Jul 1, 2003
- Hewlett-Packard Development Company
- Donald Charles Soltis
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BALANCED P-LRU TREE FOR A "MULTIPLE OF 3" NUMBER OF WAYS CACHE
- Publication number 20140215161
- Publication date Jul 31, 2014
- Adi Basel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM TO PROVIDE HIGH PERFORMANCE AND FAIRNESS IN A MULTI-THREA...
- Publication number 20140181484
- Publication date Jun 26, 2014
- James Callister
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Concurrent Control For A Page Miss Handler
- Publication number 20140075123
- Publication date Mar 13, 2014
- Gur HILDESHEIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods And Apparatuses For Reducing Step Loads Of Processors
- Publication number 20130275787
- Publication date Oct 17, 2013
- Kevin Safford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods And Apparatuses For Reducing Step Loads Of Processors
- Publication number 20110252255
- Publication date Oct 13, 2011
- Kevin Safford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatuses for reducing step loads of processors
- Publication number 20090070607
- Publication date Mar 12, 2009
- Kevin Safford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mitigating context switch cache miss penalty
- Publication number 20070067602
- Publication date Mar 22, 2007
- James R. Callister
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for responding to TLB misses
- Publication number 20070043929
- Publication date Feb 22, 2007
- Kevin Safford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods of sharing processing resources in a multi-thre...
- Publication number 20060259907
- Publication date Nov 16, 2006
- Rohit Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computer system resource access control
- Publication number 20060031679
- Publication date Feb 9, 2006
- Donald C. Soltis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resource protection in a computer system with direct hardware resou...
- Publication number 20060031672
- Publication date Feb 9, 2006
- Donald C. Soltis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Activity factor based design
- Publication number 20060009959
- Publication date Jan 12, 2006
- Timothy C. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor-architecture for facilitating a virtual machine monitor
- Publication number 20050091652
- Publication date Apr 28, 2005
- Jonathan K. Ross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for resetting and initializing an alat to a known...
- Publication number 20040083340
- Publication date Apr 29, 2004
- David P. Hannum
- G11 - INFORMATION STORAGE
Information Patent Application
Mechanism for data forwarding
- Publication number 20040062240
- Publication date Apr 1, 2004
- Eric S. Fetzer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Use sense urgency to continue with other heuristics to determine sw...
- Publication number 20030172256
- Publication date Sep 11, 2003
- Donald C. Soltis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Stacked register aliasing in data hazard detection to reduce circuit
- Publication number 20030154363
- Publication date Aug 14, 2003
- Donald C. Soltis
- G06 - COMPUTING CALCULATING COUNTING

Rohit Bhatia

Person

Patents Grantslast 30 patents

Balanced P-LRU tree for a “multiple of 3” number of ways cache

Concurrent page table walker control for TLB miss handling

Methods and apparatuses for reducing step loads of processors

Methods and apparatuses for reducing step loads of processors

Mitigating context switch cache miss penalty

Methods and apparatuses for reducing step loads of processors

Computer system resource access control

Systems and methods of sharing processing resources in a multi-thre...

Processor-architecture for facilitating a virtual machine monitor

System and method for responding to TLB misses

Using thread urgency in determining switch events in a temporal mul...

Method and apparatus for preserving pipeline data during a pipeline...

System and method for resetting and initializing a fully associativ...

Method and apparatus for efficiently generating, storing, and consu...

System and method for efficiently updating a fully associative array

Apparatus and method for conditionally flushing a pipeline upon a f...

Mechanism for data forwarding

Method and apparatus for resteering failing speculation check instr...

System and method for finding and validating the most recent advanc...

Local stall/hazard detect in superscalar, pipelined microprocessor

Local stall/hazard detect in superscalar, pipelined microprocessor...

Patents Applicationslast 30 patents

BALANCED P-LRU TREE FOR A "MULTIPLE OF 3" NUMBER OF WAYS CACHE

MECHANISM TO PROVIDE HIGH PERFORMANCE AND FAIRNESS IN A MULTI-THREA...

Concurrent Control For A Page Miss Handler

Methods And Apparatuses For Reducing Step Loads Of Processors

Methods And Apparatuses For Reducing Step Loads Of Processors

Methods and apparatuses for reducing step loads of processors

Mitigating context switch cache miss penalty

System and method for responding to TLB misses

Systems and methods of sharing processing resources in a multi-thre...

Computer system resource access control

Resource protection in a computer system with direct hardware resou...

Activity factor based design

Processor-architecture for facilitating a virtual machine monitor

System and method for resetting and initializing an alat to a known...

Mechanism for data forwarding

Use sense urgency to continue with other heuristics to determine sw...

Stacked register aliasing in data hazard detection to reduce circuit