Rohit Kapur

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Layout-aware test pattern generation and fault detection
- Patent number 11,237,210
- Issue date Feb 1, 2022
- Synopsys, Inc.
- Alodeep Sanyal
- G01 - MEASURING TESTING
Information Patent Grant
Automatically generated schematics and visualization
- Patent number 10,621,298
- Issue date Apr 14, 2020
- Synopsys, Inc.
- Anshuman Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping physical shift failures to scan cells for detecting physica...
- Patent number 10,605,863
- Issue date Mar 31, 2020
- Synopsys, Inc.
- Subhadip Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Command coverage analyzer
- Patent number 10,445,225
- Issue date Oct 15, 2019
- Synopsys, Inc.
- Chandramouli Gopalakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout-aware test pattern generation and fault detection
- Patent number 10,254,343
- Issue date Apr 9, 2019
- Synopsys, Inc.
- Alodeep Sanyal
- G01 - MEASURING TESTING
Information Patent Grant
Scheme for masking output of scan chains in test circuit
- Patent number 10,203,370
- Issue date Feb 12, 2019
- Synopsys, Inc.
- Jyotirmoy Saikia
- G01 - MEASURING TESTING
Information Patent Grant
Handling of undesirable distribution of unknown values in testing o...
- Patent number 10,067,187
- Issue date Sep 4, 2018
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Scheme for masking output of scan chains in test circuit
- Patent number 9,588,179
- Issue date Mar 7, 2017
- Synopsys, Inc.
- Jyotirmoy Saikia
- G01 - MEASURING TESTING
Information Patent Grant
Identifying failure indicating scan test cells of a circuit-under-test
- Patent number 9,568,550
- Issue date Feb 14, 2017
- Synopsys, Inc.
- Subhadip Kundu
- G01 - MEASURING TESTING
Information Patent Grant
Scheme for masking output of scan chains in test circuit
- Patent number 9,417,287
- Issue date Aug 16, 2016
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Reordering or removal of test patterns for detecting faults in inte...
- Patent number 9,411,014
- Issue date Aug 9, 2016
- Synopsys, Inc.
- Sushovan Podder
- G01 - MEASURING TESTING
Information Patent Grant
Command coverage analyzer
- Patent number 9,342,439
- Issue date May 17, 2016
- Synopsys, Inc.
- Chandramouli Gopalakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Localizing fault flop in circuit by using modified test pattern
- Patent number 9,329,235
- Issue date May 3, 2016
- Synopsys, Inc.
- Parthajit Bhattacharya
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical testing architecture using core circuit with pseudo-in...
- Patent number 9,239,897
- Issue date Jan 19, 2016
- Synopsys, Inc.
- Subramanian B. Chebiyam
- G01 - MEASURING TESTING
Information Patent Grant
Test design optimizer for configurable scan architectures
- Patent number 8,954,918
- Issue date Feb 10, 2015
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Systemic diagnostics for increasing wafer yield
- Patent number 8,660,818
- Issue date Feb 25, 2014
- Synopsys, Inc.
- Rohit Kapur
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Test design optimizer for configurable scan architectures
- Patent number 8,584,073
- Issue date Nov 12, 2013
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Accelerating automatic test pattern generation in a multi-core comp...
- Patent number 8,521,464
- Issue date Aug 27, 2013
- Synopsys, Inc.
- Ashwin Kumar
- G01 - MEASURING TESTING
Information Patent Grant
Test architecture including cyclical cache chains, selective bypass...
- Patent number 8,479,067
- Issue date Jul 2, 2013
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Implementing hierarchical design-for-test logic for modular circuit...
- Patent number 8,065,651
- Issue date Nov 22, 2011
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Dynamically reconfigurable shared scan-in test architecture
- Patent number 7,900,105
- Issue date Mar 1, 2011
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Dynamically reconfigurable shared scan-in test architecture
- Patent number 7,836,367
- Issue date Nov 16, 2010
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Dynamically reconfigurable shared scan-in test architecture
- Patent number 7,836,368
- Issue date Nov 16, 2010
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Scan compression circuit and method of design therefor
- Patent number 7,814,444
- Issue date Oct 12, 2010
- Synopsys, Inc.
- Peter Wohl
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Slack-based transition-fault testing
- Patent number 7,797,601
- Issue date Sep 14, 2010
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Dynamically reconfigurable shared scan-in test architecture
- Patent number 7,774,663
- Issue date Aug 10, 2010
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Dynamically reconfigurable shared scan-in test architecture
- Patent number 7,743,299
- Issue date Jun 22, 2010
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for limiting power dissipation in test
- Patent number 7,669,098
- Issue date Feb 23, 2010
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Dynamically reconfigurable shared scan-in test architecture
- Patent number 7,596,733
- Issue date Sep 29, 2009
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Slack-based transition-fault testing
- Patent number 7,546,500
- Issue date Jun 9, 2009
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
MAPPING PHYSICAL SHIFT FAILURES TO SCAN CELLS FOR DETECTING PHYSICA...
- Publication number 20180267098
- Publication date Sep 20, 2018
- Synopsys, Inc.
- Subhadip Kundu
- G01 - MEASURING TESTING
Information Patent Application
AUTOMATICALLY GENERATED SCHEMATICS AND VISUALIZATION
- Publication number 20170116364
- Publication date Apr 27, 2017
- Synopsys, Inc.
- Anshuman Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IDENTIFYING FAILURE INDICATING SCAN TEST CELLS OF A CIRCUIT-UNDER-TEST
- Publication number 20170059651
- Publication date Mar 2, 2017
- Synopsys, Inc.
- Subhadip Kundu
- G01 - MEASURING TESTING
Information Patent Application
Scheme for Masking Output of Scan Chains in Test Circuit
- Publication number 20160341795
- Publication date Nov 24, 2016
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
COMMAND COVERAGE ANALYZER
- Publication number 20150363295
- Publication date Dec 17, 2015
- Synopsys, Inc.
- Chandramouli Gopalakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Handling of Undesirable Distribution of Unknown Values in Testing o...
- Publication number 20150025819
- Publication date Jan 22, 2015
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Scheme for Masking Output of Scan Chains in Test Circuit
- Publication number 20140372822
- Publication date Dec 18, 2014
- Jyotirmoy Saikia
- G01 - MEASURING TESTING
Information Patent Application
Scheme for Masking Output of Scan Chains in Test Circuit
- Publication number 20140317463
- Publication date Oct 23, 2014
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Hierarchical Testing Architecture Using Core Circuit with Pseudo-In...
- Publication number 20140304672
- Publication date Oct 9, 2014
- Subramanian B. Chebiyam
- G01 - MEASURING TESTING
Information Patent Application
Reordering or Removal of Test Patterns for Detecting Faults in Inte...
- Publication number 20140289579
- Publication date Sep 25, 2014
- Sushovan Podder
- G01 - MEASURING TESTING
Information Patent Application
Localizing Fault Flop in Circuit by Using Modified Test Pattern
- Publication number 20140281777
- Publication date Sep 18, 2014
- Synopsys, Inc.
- Parthajit Bhattacharya
- G01 - MEASURING TESTING
Information Patent Application
TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES
- Publication number 20140059399
- Publication date Feb 27, 2014
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
LAYOUT-AWARE TEST PATTERN GENERATION AND FAULT DETECTION
- Publication number 20140032156
- Publication date Jan 30, 2014
- Synopsys, Inc.
- Alodeep Sanyal
- G01 - MEASURING TESTING
Information Patent Application
Accelerating Automatic Test Pattern Generation in a Multi-Core Comp...
- Publication number 20110301907
- Publication date Dec 8, 2011
- Synopsys, Inc.
- Ashwin Kumar
- G01 - MEASURING TESTING
Information Patent Application
Test Architecture Including Cyclical Cache Chains, Selective Bypass...
- Publication number 20110258498
- Publication date Oct 20, 2011
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Systemic Diagnostics For Increasing Wafer Yield
- Publication number 20110040528
- Publication date Feb 17, 2011
- Synopsys, Inc.
- Rohit Kapur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamically Reconfigurable Shared Scan-In Test Architecture
- Publication number 20100223516
- Publication date Sep 2, 2010
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING A HIERARCHICAL DESIGN-FOR-TES...
- Publication number 20100192030
- Publication date Jul 29, 2010
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
Dynamically Reconfigurable Shared Scan-In Test Architecture
- Publication number 20100031101
- Publication date Feb 4, 2010
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES
- Publication number 20100017760
- Publication date Jan 21, 2010
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
Dynamically Reconfigurable Shared Scan-In Test Architecture
- Publication number 20090313514
- Publication date Dec 17, 2009
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
Dynamically Reconfigurable Shared Scan-In Test Architecture
- Publication number 20090271673
- Publication date Oct 29, 2009
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
SLACK-BASED TRANSITION-FAULT TESTING
- Publication number 20090235133
- Publication date Sep 17, 2009
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
Dynamically Reconfigurable Shared Scan-In Test Architecture
- Publication number 20080301510
- Publication date Dec 4, 2008
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
Dynamically Reconfigurable Shared Scan-In Test Architecture
- Publication number 20080294955
- Publication date Nov 27, 2008
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
Scan compression circuit and method of design therefor
- Publication number 20080256497
- Publication date Oct 16, 2008
- Synopsys, Inc.
- Peter Wohl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for limiting power dissipation in test
- Publication number 20080141188
- Publication date Jun 12, 2008
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
Slack-based transition-fault testing
- Publication number 20070206354
- Publication date Sep 6, 2007
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
Dynamically reconfigurable shared scan-in test architecture
- Publication number 20050268190
- Publication date Dec 1, 2005
- Synopsys, Inc.
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Application
Intelligent test vector formatting to reduce test vector size and a...
- Publication number 20020093356
- Publication date Jul 18, 2002
- Thomas W. Williams
- G01 - MEASURING TESTING

Rohit Kapur

Person

Patents Grantslast 30 patents

Layout-aware test pattern generation and fault detection

Automatically generated schematics and visualization

Mapping physical shift failures to scan cells for detecting physica...

Command coverage analyzer

Layout-aware test pattern generation and fault detection

Scheme for masking output of scan chains in test circuit

Handling of undesirable distribution of unknown values in testing o...

Scheme for masking output of scan chains in test circuit

Identifying failure indicating scan test cells of a circuit-under-test

Scheme for masking output of scan chains in test circuit

Reordering or removal of test patterns for detecting faults in inte...

Command coverage analyzer

Localizing fault flop in circuit by using modified test pattern

Hierarchical testing architecture using core circuit with pseudo-in...

Test design optimizer for configurable scan architectures

Systemic diagnostics for increasing wafer yield

Test design optimizer for configurable scan architectures

Accelerating automatic test pattern generation in a multi-core comp...

Test architecture including cyclical cache chains, selective bypass...

Implementing hierarchical design-for-test logic for modular circuit...

Dynamically reconfigurable shared scan-in test architecture

Dynamically reconfigurable shared scan-in test architecture

Dynamically reconfigurable shared scan-in test architecture

Scan compression circuit and method of design therefor

Slack-based transition-fault testing

Dynamically reconfigurable shared scan-in test architecture

Dynamically reconfigurable shared scan-in test architecture

Method and apparatus for limiting power dissipation in test

Dynamically reconfigurable shared scan-in test architecture

Slack-based transition-fault testing

Patents Applicationslast 30 patents

MAPPING PHYSICAL SHIFT FAILURES TO SCAN CELLS FOR DETECTING PHYSICA...

AUTOMATICALLY GENERATED SCHEMATICS AND VISUALIZATION

IDENTIFYING FAILURE INDICATING SCAN TEST CELLS OF A CIRCUIT-UNDER-TEST

Scheme for Masking Output of Scan Chains in Test Circuit

COMMAND COVERAGE ANALYZER

Handling of Undesirable Distribution of Unknown Values in Testing o...

Scheme for Masking Output of Scan Chains in Test Circuit

Scheme for Masking Output of Scan Chains in Test Circuit

Hierarchical Testing Architecture Using Core Circuit with Pseudo-In...

Reordering or Removal of Test Patterns for Detecting Faults in Inte...

Localizing Fault Flop in Circuit by Using Modified Test Pattern

TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES

LAYOUT-AWARE TEST PATTERN GENERATION AND FAULT DETECTION

Accelerating Automatic Test Pattern Generation in a Multi-Core Comp...

Test Architecture Including Cyclical Cache Chains, Selective Bypass...

Systemic Diagnostics For Increasing Wafer Yield

Dynamically Reconfigurable Shared Scan-In Test Architecture

METHOD AND APPARATUS FOR IMPLEMENTING A HIERARCHICAL DESIGN-FOR-TES...

Dynamically Reconfigurable Shared Scan-In Test Architecture

TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES

Dynamically Reconfigurable Shared Scan-In Test Architecture

Dynamically Reconfigurable Shared Scan-In Test Architecture

SLACK-BASED TRANSITION-FAULT TESTING

Dynamically Reconfigurable Shared Scan-In Test Architecture

Dynamically Reconfigurable Shared Scan-In Test Architecture

Scan compression circuit and method of design therefor

Method and apparatus for limiting power dissipation in test

Slack-based transition-fault testing

Dynamically reconfigurable shared scan-in test architecture

Intelligent test vector formatting to reduce test vector size and a...