Roland Schuetz

Person

Ottawa, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Reconfiguring through silicon vias in stacked multi-die packages
- Patent number 9,117,685
- Issue date Aug 25, 2015
- Conversant Intellectual Property Management Inc.
- Roland Schuetz
- G11 - INFORMATION STORAGE
Information Patent Grant
Serially connected memory having subdivided data interface
- Patent number 9,009,423
- Issue date Apr 14, 2015
- NovaChips Canada Inc.
- Roland Schuetz
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable module and memory subsystem
- Patent number 8,767,430
- Issue date Jul 1, 2014
- Conversant Intellectual Property Management Inc.
- Peter Gillingham
- G11 - INFORMATION STORAGE
Information Patent Grant
Single-strobe operation of memory devices
- Patent number 8,675,425
- Issue date Mar 18, 2014
- Mosaid Technologies Incorporated
- Roland Schuetz
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-chip package with pillar connection
- Patent number 8,637,984
- Issue date Jan 28, 2014
- MOSAID Technologies Incorporated
- Roland Schuetz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reconfiguring through silicon vias in stacked multi-die packages
- Patent number 8,604,593
- Issue date Dec 10, 2013
- MOSAID Technologies Incorporated
- Roland Schuetz
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-chip package with thermal frame and method of assembling
- Patent number 8,587,111
- Issue date Nov 19, 2013
- MOSAID Technologies Incorporated
- Roland Schuetz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Configurable module and memory subsystem
- Patent number 8,503,211
- Issue date Aug 6, 2013
- Mosaid Technologies Incorporated
- Peter Gillingham
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems for failure isolation and data recovery in a co...
- Patent number 8,443,233
- Issue date May 14, 2013
- Mosaid Technologies Incorporated
- Roland Schuetz
- G11 - INFORMATION STORAGE
Information Patent Grant
Single-strobe operation of memory devices
- Patent number 8,406,070
- Issue date Mar 26, 2013
- Mosaid Technologies Incorporated
- Roland Schuetz
- G11 - INFORMATION STORAGE
Information Patent Grant
Single-strobe operation of memory devices
- Patent number 7,889,578
- Issue date Feb 15, 2011
- MOSAID Technologies Incorporated
- Roland Schuetz
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems for failure isolation and data recovery in a co...
- Patent number 7,836,340
- Issue date Nov 16, 2010
- Mosaid Technologies Incorporated
- Roland Schuetz
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM HAVING ONE OR MORE MEMORY DEVICES
- Publication number 20140325178
- Publication date Oct 30, 2014
- Steven PRZYBYLSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CHIP PACKAGE WITH PILLAR CONNECTION
- Publication number 20140141566
- Publication date May 22, 2014
- MOSAID TECHNOLOGIES INCORPORATED
- Roland SCHUETZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES
- Publication number 20140097891
- Publication date Apr 10, 2014
- Roland Schuetz
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURABLE MODULE AND MEMORY SUBSYSTEM
- Publication number 20130322173
- Publication date Dec 5, 2013
- MOSAID TECHNOLOGIES INCORPORATED
- Peter Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE-STROBE OPERATION OF MEMORY DEVICES
- Publication number 20130201775
- Publication date Aug 8, 2013
- MOSAID TECHNOLOGIES INCORPORATED
- Roland Schuetz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONNECTION OF MULTIPLE SEMICONDUCTOR MEMORY DEVICES WITH CHIP ENABL...
- Publication number 20130094271
- Publication date Apr 18, 2013
- MOSAID TECHNOLOGIES INCORPORATED
- Roland SCHUETZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SERIALLY CONNECTED MEMORY HAVING SUBDIVIDED DATA INTERFACE
- Publication number 20130086334
- Publication date Apr 4, 2013
- MOSAID TECHNOLOGIES INCORPORATED
- Roland SCHUETZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CHIP PACKAGE WITH THERMAL FRAME AND METHOD OF ASSEMBLING
- Publication number 20120001314
- Publication date Jan 5, 2012
- MOSAID TECHNOLOGIES INCORPORATED
- Roland SCHUETZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP PACKAGE WITH PILLAR CONNECTION
- Publication number 20110298128
- Publication date Dec 8, 2011
- MOSAID TECHNOLOGIES INCORPORATED
- Roland SCHUETZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR CONCURRENTLY READING A PLURALITY OF MEMORY...
- Publication number 20110276775
- Publication date Nov 10, 2011
- MOSAID TECHNOLOGIES INCORPORATED
- Roland SCHUETZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATUS INDICATION IN A SYSTEM HAVING A PLURALITY OF MEMORY DEVICES
- Publication number 20110258366
- Publication date Oct 20, 2011
- MOSAID TECHNOLOGIES INCORPORATED
- Roland Schuetz
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE-STROBE OPERATION OF MEMORY DEVICES
- Publication number 20110096614
- Publication date Apr 28, 2011
- MOSAID TECHNOLOGIES INCORPORATED
- Roland Schuetz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES
- Publication number 20110090004
- Publication date Apr 21, 2011
- MOSAID TECHNOLOGIES INCORPORATED
- Roland Schuetz
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND SYSTEMS FOR FAILURE ISOLATION AND DATA RECOVERY IN A CO...
- Publication number 20110060937
- Publication date Mar 10, 2011
- Roland SCHUETZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE MODULE AND MEMORY SUBSYSTEM
- Publication number 20100296256
- Publication date Nov 25, 2010
- MOSAID TECHNOLOGIES INCORPORATED
- Peter Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR FAILURE ISOLATION AND DATA RECOVERY IN A CO...
- Publication number 20090129184
- Publication date May 21, 2009
- Mosaid Technologies Incorporated
- Roland SCHUETZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE-STROBE OPERATION OF MEMORY DEVICES
- Publication number 20090103378
- Publication date Apr 23, 2009
- MOSAID Technologies Incorporated
- Roland Schuetz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM HAVING ONE OR MORE MEMORY DEVICES
- Publication number 20080201548
- Publication date Aug 21, 2008
- MOSAID Technologies Incorporated
- Steven PRZYBYLSKI
- G06 - COMPUTING CALCULATING COUNTING

Roland Schuetz

Person

Patents Grantslast 30 patents

Reconfiguring through silicon vias in stacked multi-die packages

Serially connected memory having subdivided data interface

Configurable module and memory subsystem

Single-strobe operation of memory devices

Multi-chip package with pillar connection

Reconfiguring through silicon vias in stacked multi-die packages

Multi-chip package with thermal frame and method of assembling

Configurable module and memory subsystem

Methods and systems for failure isolation and data recovery in a co...

Single-strobe operation of memory devices

Single-strobe operation of memory devices

Methods and systems for failure isolation and data recovery in a co...

Patents Applicationslast 30 patents

SYSTEM HAVING ONE OR MORE MEMORY DEVICES

MULTI-CHIP PACKAGE WITH PILLAR CONNECTION

RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES

CONFIGURABLE MODULE AND MEMORY SUBSYSTEM

SINGLE-STROBE OPERATION OF MEMORY DEVICES

CONNECTION OF MULTIPLE SEMICONDUCTOR MEMORY DEVICES WITH CHIP ENABL...

SERIALLY CONNECTED MEMORY HAVING SUBDIVIDED DATA INTERFACE

MULTI-CHIP PACKAGE WITH THERMAL FRAME AND METHOD OF ASSEMBLING

MULTI-CHIP PACKAGE WITH PILLAR CONNECTION

METHOD AND APPARATUS FOR CONCURRENTLY READING A PLURALITY OF MEMORY...

STATUS INDICATION IN A SYSTEM HAVING A PLURALITY OF MEMORY DEVICES

SINGLE-STROBE OPERATION OF MEMORY DEVICES

RECONFIGURING THROUGH SILICON VIAS IN STACKED MULTI-DIE PACKAGES

METHODS AND SYSTEMS FOR FAILURE ISOLATION AND DATA RECOVERY IN A CO...

CONFIGURABLE MODULE AND MEMORY SUBSYSTEM

METHODS AND SYSTEMS FOR FAILURE ISOLATION AND DATA RECOVERY IN A CO...

SINGLE-STROBE OPERATION OF MEMORY DEVICES

SYSTEM HAVING ONE OR MORE MEMORY DEVICES