Rolf Sautter

Person

Bondorf, DE

People

Patents Grantslast 30 patents

Information Patent Grant
True complement dynamic circuit and method for combining binary data
- Patent number 11,881,853
- Issue date Jan 23, 2024
- International Business Machines Corporation
- Michael Berthold Kugel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit including logic circuitry
- Patent number 11,328,110
- Issue date May 10, 2022
- International Business Machines Corporation
- Juergen Pille
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with vertical structures on nodes of a grid
- Patent number 11,171,142
- Issue date Nov 9, 2021
- International Business Machines Corporation
- Juergen Pille
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic device with a memory element utilizing stacked vert...
- Patent number 11,164,879
- Issue date Nov 2, 2021
- International Business Machines Corporation
- Juergen Pille
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout of a memory cell of an integrated circuit
- Patent number 10,831,970
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Rolf Sautter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buried conductive layer supplying digital circuits
- Patent number 10,833,089
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Juergen Pille
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic device utilizing stacked vertical devices
- Patent number 10,804,266
- Issue date Oct 13, 2020
- International Business Machines Corporation
- Juergen Pille
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing content addressable memory and random access memory
- Patent number 10,593,420
- Issue date Mar 17, 2020
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory cell and array
- Patent number 10,553,282
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Ananth Nag Raja Darla
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing content addressable memory and random access memory
- Patent number 10,170,199
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing content addressable memory and random access memory
- Patent number 10,079,070
- Issue date Sep 18, 2018
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure for reducing pre-charge voltage for static random-access...
- Patent number 10,002,661
- Issue date Jun 19, 2018
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Current-mode sense amplifier and reference current circuitry
- Patent number 9,767,872
- Issue date Sep 19, 2017
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure for reducing pre-charge voltage for static random-access...
- Patent number 9,727,680
- Issue date Aug 8, 2017
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure for reducing pre-charge voltage for static random-access...
- Patent number 9,721,050
- Issue date Aug 1, 2017
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure for reducing pre-charge voltage for static random-access...
- Patent number 9,721,049
- Issue date Aug 1, 2017
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory array comprising geometric footprint and...
- Patent number 9,666,278
- Issue date May 30, 2017
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Current-mode sense amplifier and reference current circuitry
- Patent number 9,564,188
- Issue date Feb 7, 2017
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory device
- Patent number 9,536,608
- Issue date Jan 3, 2017
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Transforming a phase-locked-loop generated chip clock signal to a l...
- Patent number 9,537,474
- Issue date Jan 3, 2017
- International Business Machines Corporation
- Yuen Hung Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Current-mode sense amplifier
- Patent number 9,484,073
- Issue date Nov 1, 2016
- International Business Machines Corporation
- Alexander Fritsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structure for reducing pre-charge voltage for static random-access...
- Patent number 9,431,098
- Issue date Aug 30, 2016
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical negative bitline boost write assist for SRAM memory de...
- Patent number 9,431,096
- Issue date Aug 30, 2016
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Transforming a phase-locked-loop generated chip clock signal to a l...
- Patent number 9,401,698
- Issue date Jul 26, 2016
- International Business Machines Corporation
- Yuen Hung Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Advanced array local clock buffer base block circuit
- Patent number 9,098,659
- Issue date Aug 4, 2015
- International Business Machines Corporation
- Osama Dengler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Complementary metal-oxide-semiconductor (CMOS) min/max voltage circ...
- Patent number 8,942,052
- Issue date Jan 27, 2015
- International Business Machines Corporation
- William V. Huott
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhanced power savings for memory arrays
- Patent number 8,659,963
- Issue date Feb 25, 2014
- International Business Machines Corporation
- Osama Dengler
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced power consumption memory circuitry
- Patent number 8,422,313
- Issue date Apr 16, 2013
- International Business Machines Corporation
- Stefan Buettner
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power programmable clock delay generator with integrated decode...
- Patent number 8,237,481
- Issue date Aug 7, 2012
- International Business Machines Corporation
- Yuen H. Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adder structure with midcycle latch for power reduction
- Patent number 8,086,657
- Issue date Dec 27, 2011
- International Business Machines Corporation
- Wilhelm Haller
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
TRUE COMPLEMENT DYNAMIC CIRCUIT AND METHOD FOR COMBINING BINARY DATA
- Publication number 20230060610
- Publication date Mar 2, 2023
- International Business Machines Corporation
- Michael Berthold Kugel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT INCLUDING LOGIC CIRCUITRY
- Publication number 20210312116
- Publication date Oct 7, 2021
- International Business Machines Corporation
- Juergen Pille
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF A MEMORY CELL OF AN INTEGRATED CIRCUIT
- Publication number 20200320174
- Publication date Oct 8, 2020
- International Business Machines Corporation
- Rolf Sautter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROELECTRONIC DEVICE WITH A MEMORY ELEMENT UTILIZING STACKED VERT...
- Publication number 20200161311
- Publication date May 21, 2020
- International Business Machines Corporation
- Juergen PILLE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BURIED CONDUCTIVE LAYER SUPPLYING DIGITAL CIRCUITS
- Publication number 20200161312
- Publication date May 21, 2020
- International Business Machines Corporation
- Juergen PILLE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DEVICE UTILIZING STACKED VERTICAL DEVICES
- Publication number 20200161300
- Publication date May 21, 2020
- International Business Machines Corporation
- Juergen PILLE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH VERTICAL STRUCTURES ON NODES OF A GRID
- Publication number 20200161310
- Publication date May 21, 2020
- International Business Machines Corporation
- Juergen PILLE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY
- Publication number 20180174666
- Publication date Jun 21, 2018
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY
- Publication number 20180151248
- Publication date May 31, 2018
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY
- Publication number 20180114585
- Publication date Apr 26, 2018
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Application
DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-...
- Publication number 20170243633
- Publication date Aug 24, 2017
- International Business Machines Corporation
- Alexander Fritsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-...
- Publication number 20170046465
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Alexander Fritsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-...
- Publication number 20170047112
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Application
DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-...
- Publication number 20170047111
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSFORMING A PHASE-LOCKED-LOOP GENERATED CHIP CLOCK SIGNAL TO A L...
- Publication number 20160344377
- Publication date Nov 24, 2016
- International Business Machines Corporation
- Yuen Hung CHAN
- G11 - INFORMATION STORAGE
Information Patent Application
Current-Mode Sense Amplifier and Reference Current Circuitry
- Publication number 20160336049
- Publication date Nov 17, 2016
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Application
CONTENT ADDRESSABLE MEMORY ARRAY
- Publication number 20160099053
- Publication date Apr 7, 2016
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Application
Current-Mode Sense Amplifier and Reference Current Circuitry
- Publication number 20160071555
- Publication date Mar 10, 2016
- International Business Machines Corporation
- Alexander Fritsch
- G11 - INFORMATION STORAGE
Information Patent Application
CONTENT ADDRESSABLE MEMORY CELL AND ARRAY
- Publication number 20160049198
- Publication date Feb 18, 2016
- International Business Machines Corporation
- Ananth Nag Raja Darla
- G11 - INFORMATION STORAGE
Information Patent Application
Complementary Metal-Oxide-Semiconductor (CMOS) Min/Max Voltage Circ...
- Publication number 20140140157
- Publication date May 22, 2014
- International Business Machines Corporation
- William V. Huott
- G11 - INFORMATION STORAGE
Information Patent Application
Advanced Array Local Clock Buffer Base Block Circuit
- Publication number 20140137070
- Publication date May 15, 2014
- International Business Machines Corporation
- Osama Dengler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced Power Savings for Memory Arrays
- Publication number 20130176795
- Publication date Jul 11, 2013
- International Business Machines Corporation
- Osama Dengler
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCED LEAKAGE BANKED WORDLINE HEADER
- Publication number 20130128684
- Publication date May 23, 2013
- International Business Machines Corporation
- Stefan Buettner
- G11 - INFORMATION STORAGE
Information Patent Application
Advanced Array Local Clock Buffer Base Block Circuit
- Publication number 20130091375
- Publication date Apr 11, 2013
- International Business Machines Corporation
- Osama Dengler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED POWER CONSUMPTION MEMORY CIRCUITRY
- Publication number 20120155188
- Publication date Jun 21, 2012
- International Business Machines Corporation
- Stefan Buettner
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCED PROGRAMMABLE PULSEWIDTH MODULATING CIRCUIT FOR ARRAY CLOCK...
- Publication number 20100302895
- Publication date Dec 2, 2010
- International Business Machines Corporation
- Yuen H. Chan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGAMABLE CONTROL CLOCK CIRCUIT FOR ARRAYS
- Publication number 20100164586
- Publication date Jul 1, 2010
- International Business Machines Corporation
- Rolf Sautter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low Power Programmable Clock Delay Generator with Integrated Decode...
- Publication number 20090267667
- Publication date Oct 29, 2009
- International Business Machines Corporation
- Yuen H. Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit Combining Level Shift Function with Gated Reset
- Publication number 20090058465
- Publication date Mar 5, 2009
- International Business Machines Corporation
- Thomas Froehnel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Single-ended read and differential write scheme
- Publication number 20090059688
- Publication date Mar 5, 2009
- International Business Machines Corporation
- Juergen Pille
- G11 - INFORMATION STORAGE

Rolf Sautter

Person

Patents Grantslast 30 patents

True complement dynamic circuit and method for combining binary data

Integrated circuit including logic circuitry

Integrated circuit with vertical structures on nodes of a grid

Microelectronic device with a memory element utilizing stacked vert...

Layout of a memory cell of an integrated circuit

Buried conductive layer supplying digital circuits

Microelectronic device utilizing stacked vertical devices

Testing content addressable memory and random access memory

Content addressable memory cell and array

Testing content addressable memory and random access memory

Testing content addressable memory and random access memory

Structure for reducing pre-charge voltage for static random-access...

Current-mode sense amplifier and reference current circuitry

Structure for reducing pre-charge voltage for static random-access...

Structure for reducing pre-charge voltage for static random-access...

Structure for reducing pre-charge voltage for static random-access...

Content addressable memory array comprising geometric footprint and...

Current-mode sense amplifier and reference current circuitry

Content addressable memory device

Transforming a phase-locked-loop generated chip clock signal to a l...

Current-mode sense amplifier

Structure for reducing pre-charge voltage for static random-access...

Hierarchical negative bitline boost write assist for SRAM memory de...

Transforming a phase-locked-loop generated chip clock signal to a l...

Advanced array local clock buffer base block circuit

Complementary metal-oxide-semiconductor (CMOS) min/max voltage circ...

Enhanced power savings for memory arrays

Reduced power consumption memory circuitry

Low power programmable clock delay generator with integrated decode...

Adder structure with midcycle latch for power reduction

Patents Applicationslast 30 patents

TRUE COMPLEMENT DYNAMIC CIRCUIT AND METHOD FOR COMBINING BINARY DATA

INTEGRATED CIRCUIT INCLUDING LOGIC CIRCUITRY

LAYOUT OF A MEMORY CELL OF AN INTEGRATED CIRCUIT

MICROELECTRONIC DEVICE WITH A MEMORY ELEMENT UTILIZING STACKED VERT...

BURIED CONDUCTIVE LAYER SUPPLYING DIGITAL CIRCUITS

MICROELECTRONIC DEVICE UTILIZING STACKED VERTICAL DEVICES

INTEGRATED CIRCUIT WITH VERTICAL STRUCTURES ON NODES OF A GRID

TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY

TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY

TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY

DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-...

DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-...

DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-...

DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-...

TRANSFORMING A PHASE-LOCKED-LOOP GENERATED CHIP CLOCK SIGNAL TO A L...

Current-Mode Sense Amplifier and Reference Current Circuitry

CONTENT ADDRESSABLE MEMORY ARRAY

Current-Mode Sense Amplifier and Reference Current Circuitry

CONTENT ADDRESSABLE MEMORY CELL AND ARRAY

Complementary Metal-Oxide-Semiconductor (CMOS) Min/Max Voltage Circ...

Advanced Array Local Clock Buffer Base Block Circuit

Enhanced Power Savings for Memory Arrays

REDUCED LEAKAGE BANKED WORDLINE HEADER

Advanced Array Local Clock Buffer Base Block Circuit

REDUCED POWER CONSUMPTION MEMORY CIRCUITRY

ENHANCED PROGRAMMABLE PULSEWIDTH MODULATING CIRCUIT FOR ARRAY CLOCK...

PROGAMABLE CONTROL CLOCK CIRCUIT FOR ARRAYS

Low Power Programmable Clock Delay Generator with Integrated Decode...

Circuit Combining Level Shift Function with Gated Reset

Single-ended read and differential write scheme