Roman Staszewski

Person

McKinney, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
IC transmitter digital phase domain calculator with atomic computat...
- Patent number 10,911,056
- Issue date Feb 2, 2021
- Texas Instruments Incorporated
- Roman Staszewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable calculation unit with atomic computation units and c...
- Patent number 10,122,371
- Issue date Nov 6, 2018
- Texas Instruments Incorporated
- Roman Staszewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase domain calculator clock, ALU, memory, register file, sequence...
- Patent number 9,853,649
- Issue date Dec 26, 2017
- Texas Instruments Incorporated
- Roman Staszewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Software reconfigurable digital phase lock loop architecture
- Patent number 9,473,155
- Issue date Oct 18, 2016
- Texas Instruments Incorporated
- Roman Staszewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
ASIP with reconfigurable circuitry implementing atomic operations o...
- Patent number 9,116,769
- Issue date Aug 25, 2015
- Texas Instruments Incorporated
- Roman Staszewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Software reconfigurable digital phase lock loop architecture
- Patent number 8,321,489
- Issue date Nov 27, 2012
- National Semiconductor Corporation
- Roman Staszewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Fractional interpolative timing advance and retard control in a tra...
- Patent number 8,306,174
- Issue date Nov 6, 2012
- Texas Instruments Incorporated
- Thomas Casimir Murphy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Computation spreading utilizing dithering for spur reduction in a d...
- Patent number 8,134,411
- Issue date Mar 13, 2012
- Texas Instruments Incorporated
- Fuqiang Shi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Application specific instruction set processor for digital radio pr...
- Patent number 8,065,506
- Issue date Nov 22, 2011
- Texas Instruments Incorporated
- Jinwen Xi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computation spreading for spur reduction in a digital phase lock loop
- Patent number 7,936,221
- Issue date May 3, 2011
- Texas Instruments Incorporated
- Roman Staszewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Computation parallelization in software reconfigurable all digital...
- Patent number 7,809,927
- Issue date Oct 5, 2010
- Texas Instruments Incorporated
- Fuqiang Shi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electrically erasable programmable read only memory and method of o...
- Patent number 5,566,110
- Issue date Oct 15, 1996
- Texas Instruments Incorporated
- Eric G. Soenen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE
- Publication number 20200007134
- Publication date Jan 2, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Roman Staszewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE
- Publication number 20180083644
- Publication date Mar 22, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Roman Staszewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE
- Publication number 20170005666
- Publication date Jan 5, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Roman Staszewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE
- Publication number 20150318861
- Publication date Nov 5, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Roman Staszewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE
- Publication number 20130080495
- Publication date Mar 28, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Roman Staszewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fractional Interpolative Timing Advance and Retard Control in a Tra...
- Publication number 20100027729
- Publication date Feb 4, 2010
- Thomas Casimir Murphy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Computation spreading utilizing dithering for spur reduction in a d...
- Publication number 20090262877
- Publication date Oct 22, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Fuqiang Shi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Computation parallelization in software reconfigurable all digital...
- Publication number 20090070568
- Publication date Mar 12, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Fuqiang Shi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Application Specific Instruction Set Processor for Digital Radio Pr...
- Publication number 20090063820
- Publication date Mar 5, 2009
- Jinwen Xi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Software reconfigurable digital phase lock loop architecture
- Publication number 20080072025
- Publication date Mar 20, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Roman Staszewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computation spreading for spur reduction in a digital phase lock loop
- Publication number 20080069286
- Publication date Mar 20, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Roman Staszewski
- G06 - COMPUTING CALCULATING COUNTING

Roman Staszewski

Person

Patents Grantslast 30 patents

IC transmitter digital phase domain calculator with atomic computat...

Reconfigurable calculation unit with atomic computation units and c...

Phase domain calculator clock, ALU, memory, register file, sequence...

Software reconfigurable digital phase lock loop architecture

ASIP with reconfigurable circuitry implementing atomic operations o...

Software reconfigurable digital phase lock loop architecture

Fractional interpolative timing advance and retard control in a tra...

Computation spreading utilizing dithering for spur reduction in a d...

Application specific instruction set processor for digital radio pr...

Computation spreading for spur reduction in a digital phase lock loop

Computation parallelization in software reconfigurable all digital...

Electrically erasable programmable read only memory and method of o...

Patents Applicationslast 30 patents

SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE

SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE

SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE

SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE

SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE

Fractional Interpolative Timing Advance and Retard Control in a Tra...

Computation spreading utilizing dithering for spur reduction in a d...

Computation parallelization in software reconfigurable all digital...

Application Specific Instruction Set Processor for Digital Radio Pr...

Software reconfigurable digital phase lock loop architecture

Computation spreading for spur reduction in a digital phase lock loop