Ronald Edwin Lange

Person

Glendale, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
PCI bridge having latency inducing serial bus
- Patent number 6,581,125
- Issue date Jun 17, 2003
- Koninklijke Philips Electronics N.V.
- Ronald E. Lange
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PCI bridge configuration having physically separate parts
- Patent number 6,457,091
- Issue date Sep 24, 2002
- Koninklijke Philips Electronics N.V.
- Ronald E. Lange
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-master PCI bus system within a single integrated circuit
- Patent number 6,108,738
- Issue date Aug 22, 2000
- VLSI Technology, Inc.
- Peter Chambers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective data read-ahead in bus-to-bus bridge architecture
- Patent number 6,092,141
- Issue date Jul 18, 2000
- VLSI Technology, Inc.
- Ronald Edwin Lange
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arrangement and method for allowing sequence-independent command re...
- Patent number 6,055,598
- Issue date Apr 25, 2000
- VLSI Technology, Inc.
- Ronald Edwin Lange
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective latency reduction in bridge circuit between two busses
- Patent number 5,978,878
- Issue date Nov 2, 1999
- VLSI Technology
- Ronald Edwin Lange
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address/data queuing arrangement and method for providing high data...
- Patent number 5,941,970
- Issue date Aug 24, 1999
- VLSI Technology, Inc.
- Ronald Edwin Lange
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for reducing control store space in a VLSI central processor
- Patent number 5,894,581
- Issue date Apr 13, 1999
- Bull HN Information Systems Inc.
- Wilbur L. Stewart
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Basic operations synchronization and local mode controller in a VLS...
- Patent number 5,644,761
- Issue date Jul 1, 1997
- Bull HN Information Systems Inc.
- Ronald W. Yoder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for minimizing the number of control words in...
- Patent number 5,568,622
- Issue date Oct 22, 1996
- Bull HN Information Systems Inc.
- Wilbur Stewart
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated safestore stack generation and recovery in a fault tolera...
- Patent number 5,557,737
- Issue date Sep 17, 1996
- Bull HN Information Systems Inc.
- John E. Wilhite
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated safestore stack generation and move in a fault tolerant c...
- Patent number 5,553,232
- Issue date Sep 3, 1996
- Bull HN Informations Systems Inc.
- John E. Wilhite
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Central processor with duplicate basic processing units employing m...
- Patent number 5,515,529
- Issue date May 7, 1996
- William A. Shelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sharing of register stack by two execution units in a central proce...
- Patent number 5,507,000
- Issue date Apr 9, 1996
- Bull HN Information Systems Inc.
- Wilbur L. Stewart
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Central processor with duplicate basic processing units employing m...
- Patent number 5,495,579
- Issue date Feb 27, 1996
- Bull HN Information Systems Inc.
- William A. Shelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Central processing unit incorporation selectable, precisa ratio, sp...
- Patent number 5,367,699
- Issue date Nov 22, 1994
- Bull HN Information Systems Inc.
- Ronald E. Lange
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Safestore frame implementation in a central processor
- Patent number 5,276,862
- Issue date Jan 4, 1994
- Bull HN Information Systems Inc.
- Lowell D. McCulley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error detection in the basic processing unit of a VLSI central proc...
- Patent number 5,263,034
- Issue date Nov 16, 1993
- Bull Information Systems Inc.
- Russell W. Guenthner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary to binary coded decimal and binary coded decimal to binary c...
- Patent number 5,251,321
- Issue date Oct 5, 1993
- Bull HN Information Systems Inc.
- Donald C. Boothroyd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient error detection in a VLSI central processing unit
- Patent number 5,195,101
- Issue date Mar 16, 1993
- Bull HN Information Systems Inc.
- Russell W. Guenthner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for forcing a reload from main memory upon cache memory e...
- Patent number 4,831,622
- Issue date May 16, 1989
- Honeywell Bull Inc.
- Marion G. Porter
- G06 - COMPUTING CALCULATING COUNTING

Ronald Edwin Lange

Person

Patents Grantslast 30 patents

PCI bridge having latency inducing serial bus

PCI bridge configuration having physically separate parts

Multi-master PCI bus system within a single integrated circuit

Selective data read-ahead in bus-to-bus bridge architecture

Arrangement and method for allowing sequence-independent command re...

Selective latency reduction in bridge circuit between two busses

Address/data queuing arrangement and method for providing high data...

Method for reducing control store space in a VLSI central processor

Basic operations synchronization and local mode controller in a VLS...

Method and apparatus for minimizing the number of control words in...

Automated safestore stack generation and recovery in a fault tolera...

Automated safestore stack generation and move in a fault tolerant c...

Central processor with duplicate basic processing units employing m...

Sharing of register stack by two execution units in a central proce...

Central processor with duplicate basic processing units employing m...

Central processing unit incorporation selectable, precisa ratio, sp...

Safestore frame implementation in a central processor

Error detection in the basic processing unit of a VLSI central proc...

Binary to binary coded decimal and binary coded decimal to binary c...

Efficient error detection in a VLSI central processing unit

Apparatus for forcing a reload from main memory upon cache memory e...