Ronald Gene Walther

Person

Vestal, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for improved test controllability and observab...
- Patent number 7,882,454
- Issue date Feb 1, 2011
- International Business Machines Corporation
- Mary P Kusko
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing multi-core microprocessors
- Patent number 7,610,537
- Issue date Oct 27, 2009
- International Business Machines Corporation
- Dan Jeffrey Dickinson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for diagnosing and repairing errors in complement...
- Patent number 6,507,929
- Issue date Jan 14, 2003
- International Business Machines Corporation
- Christopher McCall Durham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for detecting errors within complementary logic c...
- Patent number 6,253,350
- Issue date Jun 26, 2001
- International Business Machines Corporation
- Christopher McCall Durham
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and method for testing high speed components using low sp...
- Patent number 6,055,658
- Issue date Apr 25, 2000
- International Business Machines Corporation
- Talal Kamel Jaber
- G01 - MEASURING TESTING
Information Patent Grant
Isolated scan paths
- Patent number 5,887,004
- Issue date Mar 23, 1999
- International Business Machines Corporation
- Ronald Gene Walther
- G01 - MEASURING TESTING
Information Patent Grant
Complete chip I/O test through low contact testing using enhanced b...
- Patent number 5,787,098
- Issue date Jul 28, 1998
- International Business Machines Corporation
- Sumit DasGupta
- G01 - MEASURING TESTING
Information Patent Grant
Level sensitive latch stage
- Patent number 4,667,339
- Issue date May 19, 1987
- Texas Instruments Incorporated
- Graham S. Tubbs
- G11 - INFORMATION STORAGE
Information Patent Grant
Latch circuit operable as a D-type edge trigger
- Patent number 4,277,699
- Issue date Jul 7, 1981
- International Business Machines Corporation
- David J. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of level sensitive testing a functional logic system with em...
- Patent number 4,074,851
- Issue date Feb 21, 1978
- International Business Machines Corporation
- Edward Baxter Eichelberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of propagation delay testing a level sensitive array logic s...
- Patent number 4,063,080
- Issue date Dec 13, 1977
- International Business Machines Corporation
- Edward Baxter Eichelberger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Level sensitive embedded array logic system
- Patent number 4,051,352
- Issue date Sep 27, 1977
- International Business Machines Corporation
- Edward Baxter Eichelberger
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR IMPROVED TEST CONTROLLABILITY AND OBSERVAB...
- Publication number 20090271671
- Publication date Oct 29, 2009
- International Business Machines Corporation
- Mary P. Kusko
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR TESTING MULTI-CORE MICROPROCESSORS
- Publication number 20070260823
- Publication date Nov 8, 2007
- Dan Jeffrey Dickinson
- G06 - COMPUTING CALCULATING COUNTING

Ronald Gene Walther

Person

Patents Grantslast 30 patents

Apparatus and method for improved test controllability and observab...

Method and apparatus for testing multi-core microprocessors

System and method for diagnosing and repairing errors in complement...

Method and system for detecting errors within complementary logic c...

Apparatus and method for testing high speed components using low sp...

Isolated scan paths

Complete chip I/O test through low contact testing using enhanced b...

Level sensitive latch stage

Latch circuit operable as a D-type edge trigger

Method of level sensitive testing a functional logic system with em...

Method of propagation delay testing a level sensitive array logic s...

Level sensitive embedded array logic system

Patents Applicationslast 30 patents

APPARATUS AND METHOD FOR IMPROVED TEST CONTROLLABILITY AND OBSERVAB...

METHOD AND APPARATUS FOR TESTING MULTI-CORE MICROPROCESSORS