Ronald J. Nagahara

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Metal planarization system
- Patent number 6,951,808
- Issue date Oct 4, 2005
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrochemical planarization end point detection
- Patent number 6,752,916
- Issue date Jun 22, 2004
- LSI Logic Corporation
- Yan Fang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of testing the processing of a semiconductor wafer on a CMP...
- Patent number 6,727,107
- Issue date Apr 27, 2004
- LSI Logic Corporation
- Samuel V. Dunton
- B24 - GRINDING POLISHING
Information Patent Grant
Process for planarization of integrated circuit structure which inh...
- Patent number 6,713,394
- Issue date Mar 30, 2004
- LSI Logic Corporation
- Ronald J. Nagahara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming planarized isolation trench in integrated circu...
- Patent number 6,607,967
- Issue date Aug 19, 2003
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal planarization system
- Patent number 6,586,326
- Issue date Jul 1, 2003
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arrangement and method for polishing a surface of a semiconductor w...
- Patent number 6,555,475
- Issue date Apr 29, 2003
- LSI Logic Corporation
- Jayanthi Pallinti
- B24 - GRINDING POLISHING
Information Patent Grant
Method and apparatus for using across wafer back pressure different...
- Patent number 6,531,397
- Issue date Mar 11, 2003
- LSI Logic Corporation
- Ronald J. Nagahara
- B24 - GRINDING POLISHING
Information Patent Grant
Process for selective polishing of metal-filled trenches of integra...
- Patent number 6,503,828
- Issue date Jan 7, 2003
- LSI Logic Corporation
- Ronald J. Nagahara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for planarization of integrated circuit structure which inh...
- Patent number 6,489,242
- Issue date Dec 3, 2002
- LSI Logic Corporation
- Ronald J. Nagahara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arrangement and method for polishing a surface of a semiconductor w...
- Patent number 6,439,981
- Issue date Aug 27, 2002
- LSI Logic Corporation
- Jayanthi Pallinti
- B24 - GRINDING POLISHING
Information Patent Grant
Process for planarization of metal-filled trenches of integrated ci...
- Patent number 6,417,093
- Issue date Jul 9, 2002
- LSI Logic Corporation
- James J. Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for CMP endpoint detection
- Patent number 6,372,524
- Issue date Apr 16, 2002
- LSI Logic Corporation
- James J. Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for using across wafer back pressure different...
- Patent number 6,179,956
- Issue date Jan 30, 2001
- LSI Logic Corporation
- Ronald J. Nagahara
- B24 - GRINDING POLISHING
Information Patent Grant
Polishing pad surface for improved process control
- Patent number 6,168,508
- Issue date Jan 2, 2001
- LSI Logic Corporation
- Ronald J. Nagahara
- B24 - GRINDING POLISHING
Information Patent Grant
Generating non-planar topology on the surface of planar and near-pl...
- Patent number 6,114,215
- Issue date Sep 5, 2000
- LSI Logic Corporation
- Richard S. Osugi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Effective pad conditioning
- Patent number 6,106,371
- Issue date Aug 22, 2000
- LSI Logic Corporation
- Ronald J. Nagahara
- B24 - GRINDING POLISHING
Information Patent Grant
Modified carrier films to produce more uniformly polished substrate...
- Patent number 6,074,288
- Issue date Jun 13, 2000
- LSI Logic Corporation
- Ronald J. Nagahara
- B24 - GRINDING POLISHING
Information Patent Grant
In-situ chemical-mechanical polishing slurry formulation for compen...
- Patent number 6,066,266
- Issue date May 23, 2000
- LSI Logic Corporation
- Richard S. Osugi
- B24 - GRINDING POLISHING
Information Patent Grant
Dual purpose retaining ring and polishing pad conditioner
- Patent number 6,004,193
- Issue date Dec 21, 1999
- LSI Logic Corporation
- Ron J. Nagahara
- B24 - GRINDING POLISHING
Information Patent Grant
Shimming substrate holder assemblies to produce more uniformly poli...
- Patent number 5,961,375
- Issue date Oct 5, 1999
- LSI Logic Corporation
- Ronald J. Nagahara
- B24 - GRINDING POLISHING
Information Patent Grant
Use of abrasive tape conveying assemblies for conditioning polishin...
- Patent number 5,944,585
- Issue date Aug 31, 1999
- LSI Logic Corporation
- Ronald J. Nagahara
- B24 - GRINDING POLISHING
Information Patent Grant
Shaping polishing pad to control material removal rate selectively
- Patent number 5,941,761
- Issue date Aug 24, 1999
- LSI Logic Corporation
- Ronald J. Nagahara
- B24 - GRINDING POLISHING
Information Patent Grant
Method and apparatus for using pressure differentials through a pol...
- Patent number 5,931,719
- Issue date Aug 3, 1999
- LSI Logic Corporation
- Ronald J. Nagahara
- B24 - GRINDING POLISHING
Information Patent Grant
Apparatus and method for polish removing a precise amount of materi...
- Patent number 5,865,666
- Issue date Feb 2, 1999
- LSI Logic Corporation
- Ron J. Nagahara
- B24 - GRINDING POLISHING
Information Patent Grant
Apparatus for polishing a substrate at radially varying polish rates
- Patent number 5,816,900
- Issue date Oct 6, 1998
- LSI Logic Corporation
- Ron J. Nagahara
- B24 - GRINDING POLISHING

Patents Applicationslast 30 patents

Information Patent Application
Metal planarization system
- Publication number 20040018719
- Publication date Jan 29, 2004
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for planarization of integrated circuit structure which inh...
- Publication number 20030017704
- Publication date Jan 23, 2003
- Ronald J. Nagahara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal planarization system
- Publication number 20020132470
- Publication date Sep 19, 2002
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS

Ronald J. Nagahara

Person

Patents Grantslast 30 patents

Metal planarization system

Electrochemical planarization end point detection

Method of testing the processing of a semiconductor wafer on a CMP...

Process for planarization of integrated circuit structure which inh...

Process for forming planarized isolation trench in integrated circu...

Metal planarization system

Arrangement and method for polishing a surface of a semiconductor w...

Method and apparatus for using across wafer back pressure different...

Process for selective polishing of metal-filled trenches of integra...

Process for planarization of integrated circuit structure which inh...

Arrangement and method for polishing a surface of a semiconductor w...

Process for planarization of metal-filled trenches of integrated ci...

Method for CMP endpoint detection

Method and apparatus for using across wafer back pressure different...

Polishing pad surface for improved process control

Generating non-planar topology on the surface of planar and near-pl...

Effective pad conditioning

Modified carrier films to produce more uniformly polished substrate...

In-situ chemical-mechanical polishing slurry formulation for compen...

Dual purpose retaining ring and polishing pad conditioner

Shimming substrate holder assemblies to produce more uniformly poli...

Use of abrasive tape conveying assemblies for conditioning polishin...

Shaping polishing pad to control material removal rate selectively

Method and apparatus for using pressure differentials through a pol...

Apparatus and method for polish removing a precise amount of materi...

Apparatus for polishing a substrate at radially varying polish rates

Patents Applicationslast 30 patents

Metal planarization system

Process for planarization of integrated circuit structure which inh...

Metal planarization system