Ronald P. Hall

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Virtual channel support using write table
- Patent number 11,893,413
- Issue date Feb 6, 2024
- Apple Inc.
- Michael D. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prediction confirmation for cache subsystem
- Patent number 11,880,308
- Issue date Jan 23, 2024
- Apple Inc.
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prediction confirmation for cache subsystem
- Patent number 11,487,667
- Issue date Nov 1, 2022
- Apple Inc.
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to ensure forward progress of a processor in the presence of...
- Patent number 11,080,188
- Issue date Aug 3, 2021
- Apple Inc.
- Jonathan Y. Tong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fetch predition circuit for reducing power consumption in a processor
- Patent number 10,901,484
- Issue date Jan 26, 2021
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache flush method and apparatus
- Patent number 10,552,323
- Issue date Feb 4, 2020
- Apple Inc.
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accessing memories in coherent and non-coherent domains in a comput...
- Patent number 10,402,326
- Issue date Sep 3, 2019
- Apple Inc.
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing power consumption in a processor
- Patent number 10,241,557
- Issue date Mar 26, 2019
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Immediate branch recode that handles aliasing
- Patent number 9,940,262
- Issue date Apr 10, 2018
- Apple Inc.
- Shyam Sundar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retrieving instructions of a single branch, backwards short loop fr...
- Patent number 9,772,851
- Issue date Sep 26, 2017
- International Business Machines Corporation
- Ronald Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffering instructions of a single branch, backwards short loop wit...
- Patent number 9,632,788
- Issue date Apr 25, 2017
- International Business Machines Corporation
- Ronald Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache for patterns of instructions with multiple forward control tr...
- Patent number 9,632,791
- Issue date Apr 25, 2017
- Apple Inc.
- Muawya M. Al-Otoom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction loop buffer with tiered power savings
- Patent number 9,524,011
- Issue date Dec 20, 2016
- Apple Inc.
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction swap for patching problematic instructions in a micropr...
- Patent number 9,395,992
- Issue date Jul 19, 2016
- International Business Machines Corporation
- Richard W. Doing
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retrieving instructions of a single branch, backwards short loop fr...
- Patent number 9,395,995
- Issue date Jul 19, 2016
- International Business Machines Corporation
- Ronald Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for reducing cache power consumption using cache way pred...
- Patent number 9,311,098
- Issue date Apr 12, 2016
- Apple Inc.
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficiency of short loop instruction fetch
- Patent number 9,052,910
- Issue date Jun 9, 2015
- International Business Machines Corporation
- Ronald Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware assist thread for increasing code parallelism
- Patent number 9,037,837
- Issue date May 19, 2015
- International Business Machines Corporation
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Obtaining and releasing hardware threads without hypervisor involve...
- Patent number 8,898,441
- Issue date Nov 25, 2014
- International Business Machines Corporation
- Giles Roger Frazier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Obtaining and releasing hardware threads without hypervisor involve...
- Patent number 8,793,474
- Issue date Jul 29, 2014
- International Business Machines Corporation
- Giles Roger Frazier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scaleable status tracking of multiple assist hardware threads
- Patent number 8,719,554
- Issue date May 6, 2014
- International Business Machines Corporation
- Richard Louis Arndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scaleable status tracking of multiple assist hardware threads
- Patent number 8,713,290
- Issue date Apr 29, 2014
- International Business Machines Corporation
- Richard Louis Arndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware assist thread for dynamic performance profiling
- Patent number 8,612,730
- Issue date Dec 17, 2013
- International Business Machines Corporation
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware assist thread for increasing code parallelism
- Patent number 8,423,750
- Issue date Apr 16, 2013
- International Business Machines Corporation
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Issue unit for placing a processor into a gradual slow mode of oper...
- Patent number 8,200,946
- Issue date Jun 12, 2012
- International Business Machines Corporation
- Christopher M. Abernathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for dynamic livelock resolution with variable delay memor...
- Patent number 8,131,980
- Issue date Mar 6, 2012
- International Business Machines Corporation
- Ronald Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance of an in-order processor by no longer requiring a unifo...
- Patent number 8,028,151
- Issue date Sep 27, 2011
- International Business Machines Corporation
- Christopher Michael Abernathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Time-of-life counter for handling instruction flushes from a queue
- Patent number 7,913,070
- Issue date Mar 22, 2011
- International Business Machines Corporation
- Christopher Michael Abernathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling data cache misses out-of-order for asynchronous pipelines
- Patent number 7,900,024
- Issue date Mar 1, 2011
- International Business Machines Corporation
- Christopher M. Abernathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable link stack control method with full support for speculativ...
- Patent number 7,900,027
- Issue date Mar 1, 2011
- International Business Machines Corporation
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Trace Cache Techniques Based on Biased Control Transfer Instructions
- Publication number 20250021332
- Publication date Jan 16, 2025
- Apple Inc.
- Niket K. Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Trace Cache with Filter for Internal Control Transfer Inclusion
- Publication number 20250021333
- Publication date Jan 16, 2025
- Apple Inc.
- Ilhyun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prediction Confirmation for Cache Subsystem
- Publication number 20240176744
- Publication date May 30, 2024
- Apple Inc.
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using a Next Fetch Predictor Circuit with Short Branches and Return...
- Publication number 20240028339
- Publication date Jan 25, 2024
- Apple Inc.
- Niket K. Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prediction Confirmation for Cache Subsystem
- Publication number 20230084736
- Publication date Mar 16, 2023
- Apple Inc.
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Virtual Channel Support Using Write Table
- Publication number 20220083369
- Publication date Mar 17, 2022
- Apple Inc.
- Michael D. Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING POWER CONSUMPTION IN A PROCESSOR
- Publication number 20190286218
- Publication date Sep 19, 2019
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENCY OF AN INSTRUCTION CACHE BY RETRIEVING INSTRUCTIONS FOR C...
- Publication number 20160216970
- Publication date Jul 28, 2016
- International Business Machines Corporation
- Ronald Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMMEDIATE BRANCH RECODE THAT HANDLES ALIASING
- Publication number 20160085550
- Publication date Mar 24, 2016
- Apple Inc.
- Shyam Sundar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION LOOP BUFFER WITH TIERED POWER SAVINGS
- Publication number 20150293577
- Publication date Oct 15, 2015
- Apple Inc.
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE FOR PATTERNS OF INSTRUCTIONS
- Publication number 20150205725
- Publication date Jul 23, 2015
- Apple Inc.
- Muawya M. Al-Otoom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING POWER CONSUMPTION IN A PROCESSOR
- Publication number 20150169041
- Publication date Jun 18, 2015
- Apple Inc.
- Conrado Blasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for Reducing Cache Power Consumption Using Cache Way Pred...
- Publication number 20140337605
- Publication date Nov 13, 2014
- Apple Inc.
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION SWAP FOR PATCHING PROBLEMATIC INSTRUCTIONS IN A MICROPR...
- Publication number 20140143521
- Publication date May 22, 2014
- International Business Machines Corporation
- Richard W. Doing
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scaleable Status Tracking Of Multiple Assist Hardware Threads
- Publication number 20130139168
- Publication date May 30, 2013
- International Business Machines Corporation
- Richard Louis Arndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hardware Assist Thread for Increasing Code Parallelism
- Publication number 20120254594
- Publication date Oct 4, 2012
- International Business Machines Corporation
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Obtaining And Releasing Hardware Threads Without Hypervisor Involve...
- Publication number 20120210102
- Publication date Aug 16, 2012
- International Business Machines Corporation
- Giles Roger Frazier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENCY OF SHORT LOOP INSTRUCTION FETCH
- Publication number 20120159125
- Publication date Jun 21, 2012
- International Business Machines Corporation
- Ronald D. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Obtaining And Releasing Hardware Threads Without Hypervisor Involve...
- Publication number 20120072705
- Publication date Mar 22, 2012
- International Business Machines Corporation
- Giles Roger Frazier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scaleable Status Tracking Of Multiple Assist Hardware Threads
- Publication number 20120072707
- Publication date Mar 22, 2012
- International Business Machines Corporation
- Richard Louis Arndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hardware Assist for Optimizing Code During Processing
- Publication number 20120005462
- Publication date Jan 5, 2012
- International Business Machines Corporation
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ASSIST THREAD FOR DYNAMIC PERFORMANCE PROFILING
- Publication number 20110302395
- Publication date Dec 8, 2011
- International Business Machines Corporation
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hardware Assist Thread for Increasing Code Parallelism
- Publication number 20110283095
- Publication date Nov 17, 2011
- International Business Machines Corporation
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE LINK STACK CONTROL METHOD WITH FULL SUPPORT FOR SPECULATIV...
- Publication number 20090198959
- Publication date Aug 6, 2009
- Ronald P. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR IMPROVING EFFICIENCY OF SHORT LOOP INSTRUCTION...
- Publication number 20090113192
- Publication date Apr 30, 2009
- Ronald Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method for Improving Efficiency of Short Loop Instruc...
- Publication number 20090113191
- Publication date Apr 30, 2009
- Ronald Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMANCE OF AN IN-ORDER PROCESSOR BY NO LONGER REQUIRING A UNIFO...
- Publication number 20090077352
- Publication date Mar 19, 2009
- International Business Machines Corporation
- Christopher Michael Abernathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Handling Data Cache Misses Out-of-Order for Asynchronous Pipelines
- Publication number 20090043995
- Publication date Feb 12, 2009
- International Business Machines Corporation
- Christopher M. Abernathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Time-Of-Life Counter For Handling Instruction Flushes From A Queue
- Publication number 20090043997
- Publication date Feb 12, 2009
- International Business Machines Corporation
- Christopher Michael Abernathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanisms for Placing a Processor into a Gradual Slow Mode of Oper...
- Publication number 20090006817
- Publication date Jan 1, 2009
- International Business Machines Corporation
- Christopher M. Abernathy
- G06 - COMPUTING CALCULATING COUNTING

Ronald P. Hall

Person

Patents Grantslast 30 patents

Virtual channel support using write table

Prediction confirmation for cache subsystem

Prediction confirmation for cache subsystem

Method to ensure forward progress of a processor in the presence of...

Fetch predition circuit for reducing power consumption in a processor

Cache flush method and apparatus

Accessing memories in coherent and non-coherent domains in a comput...

Reducing power consumption in a processor

Immediate branch recode that handles aliasing

Retrieving instructions of a single branch, backwards short loop fr...

Buffering instructions of a single branch, backwards short loop wit...

Cache for patterns of instructions with multiple forward control tr...

Instruction loop buffer with tiered power savings

Instruction swap for patching problematic instructions in a micropr...

Retrieving instructions of a single branch, backwards short loop fr...

Mechanism for reducing cache power consumption using cache way pred...

Efficiency of short loop instruction fetch

Hardware assist thread for increasing code parallelism

Obtaining and releasing hardware threads without hypervisor involve...

Obtaining and releasing hardware threads without hypervisor involve...

Scaleable status tracking of multiple assist hardware threads

Scaleable status tracking of multiple assist hardware threads

Hardware assist thread for dynamic performance profiling

Hardware assist thread for increasing code parallelism

Issue unit for placing a processor into a gradual slow mode of oper...

Structure for dynamic livelock resolution with variable delay memor...

Performance of an in-order processor by no longer requiring a unifo...

Time-of-life counter for handling instruction flushes from a queue

Handling data cache misses out-of-order for asynchronous pipelines

Scalable link stack control method with full support for speculativ...

Patents Applicationslast 30 patents

Trace Cache Techniques Based on Biased Control Transfer Instructions

Trace Cache with Filter for Internal Control Transfer Inclusion

Prediction Confirmation for Cache Subsystem

Using a Next Fetch Predictor Circuit with Short Branches and Return...

Prediction Confirmation for Cache Subsystem

Virtual Channel Support Using Write Table

REDUCING POWER CONSUMPTION IN A PROCESSOR

EFFICIENCY OF AN INSTRUCTION CACHE BY RETRIEVING INSTRUCTIONS FOR C...

IMMEDIATE BRANCH RECODE THAT HANDLES ALIASING

INSTRUCTION LOOP BUFFER WITH TIERED POWER SAVINGS

CACHE FOR PATTERNS OF INSTRUCTIONS

REDUCING POWER CONSUMPTION IN A PROCESSOR

Mechanism for Reducing Cache Power Consumption Using Cache Way Pred...

INSTRUCTION SWAP FOR PATCHING PROBLEMATIC INSTRUCTIONS IN A MICROPR...

Scaleable Status Tracking Of Multiple Assist Hardware Threads

Hardware Assist Thread for Increasing Code Parallelism

Obtaining And Releasing Hardware Threads Without Hypervisor Involve...

EFFICIENCY OF SHORT LOOP INSTRUCTION FETCH

Obtaining And Releasing Hardware Threads Without Hypervisor Involve...

Scaleable Status Tracking Of Multiple Assist Hardware Threads

Hardware Assist for Optimizing Code During Processing

HARDWARE ASSIST THREAD FOR DYNAMIC PERFORMANCE PROFILING

Hardware Assist Thread for Increasing Code Parallelism

SCALABLE LINK STACK CONTROL METHOD WITH FULL SUPPORT FOR SPECULATIV...

DESIGN STRUCTURE FOR IMPROVING EFFICIENCY OF SHORT LOOP INSTRUCTION...

Apparatus and Method for Improving Efficiency of Short Loop Instruc...

PERFORMANCE OF AN IN-ORDER PROCESSOR BY NO LONGER REQUIRING A UNIFO...

Handling Data Cache Misses Out-of-Order for Asynchronous Pipelines

Time-Of-Life Counter For Handling Instruction Flushes From A Queue

Mechanisms for Placing a Processor into a Gradual Slow Mode of Oper...