Ronald Pasqualini

Person

Los Altos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of stitching scan flipflops together to form a scan chain wi...
- Patent number 7,996,805
- Issue date Aug 9, 2011
- National Semiconductor Corporation
- Ronald Pasqualini
- G01 - MEASURING TESTING
Information Patent Grant
ESD structure that protects against power-on and power-off ESD event
- Patent number 7,978,454
- Issue date Jul 12, 2011
- National Semiconductor Corporation
- Ronald Pasqualini
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
High voltage CMOS output buffer constructed from low voltage CMOS t...
- Patent number 7,863,962
- Issue date Jan 4, 2011
- National Semiconductor Corporation
- Ronald Pasqualini
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Floating diodes
- Patent number 7,723,792
- Issue date May 25, 2010
- National Semiconductor Corporation
- Ronald Pasqualini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PECL/LVPECL input buffer that employs positive feedback to provide...
- Patent number 7,633,311
- Issue date Dec 15, 2009
- National Semiconductor Corporation
- Ronald Pasqualini
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Wideband power-on reset circuit
- Patent number 7,518,419
- Issue date Apr 14, 2009
- National Semiconductor Corporation
- Ronald Pasqualini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed, low power, pipelined zero crossing detector that utiliz...
- Patent number 7,424,507
- Issue date Sep 9, 2008
- National Semiconductor Corporation
- Ronald Pasqualini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wideband power-on reset circuit with glitch-free output
- Patent number 7,388,414
- Issue date Jun 17, 2008
- National Semiconductor Corporation
- Ronald Pasqualini
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flipflop that can tolerate arbitrarily slow clock edges
- Patent number 7,265,599
- Issue date Sep 4, 2007
- National Semiconductor Corporation
- Ronald Pasqualini
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and metric for low power standard cell logic synthesis
- Patent number 7,260,808
- Issue date Aug 21, 2007
- National Semiconductor Corporation
- Ronald Pasqualini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed, universal polarity full adder which consumes minimal po...
- Patent number 7,185,042
- Issue date Feb 27, 2007
- National Semiconductor Corporation
- Ronald Pasqualini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power, high speed logic controller that implements thermometer-...
- Patent number 7,109,747
- Issue date Sep 19, 2006
- National Semiconductor Corporation
- Ronald Pasqualini
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed synchronizer for simultaneously initializing rising edge...
- Patent number 7,098,706
- Issue date Aug 29, 2006
- National Semiconductor Corporation
- Ronald Pasqualini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gated clock circuit with a substantially increased control signal d...
- Patent number 7,042,267
- Issue date May 9, 2006
- National Semiconductor Corporation
- Ronald Pasqualini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ESD protection circuit that can tolerate a negative input voltage d...
- Patent number 7,038,898
- Issue date May 2, 2006
- National Semiconductor Corporation
- Ronald Pasqualini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low power, minimal area tap multiplier
- Patent number 6,981,013
- Issue date Dec 27, 2005
- National Semiconductor Corporation
- Ronald Pasqualini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ESD protection circuit utilizing floating lateral clamp diodes
- Patent number 6,977,420
- Issue date Dec 20, 2005
- National Semiconductor Corporation
- Ronald Pasqualini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with low inductance ground path and impr...
- Patent number 6,710,432
- Issue date Mar 23, 2004
- National Semiconductor Corporation
- Ronald Pasqualini
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Electrostatic discharge protection circuit with cascoded trigger-sw...
- Patent number 6,690,555
- Issue date Feb 10, 2004
- National Semiconductor Corporation
- Ronald Pasqualini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip flop which has complementary, symmetric, minimal timing skew o...
- Patent number 6,492,855
- Issue date Dec 10, 2002
- National Semiconductor Corporation
- Ronald Pasqualini
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed, low power, minimal area double edge triggered flip flop
- Patent number 6,489,825
- Issue date Dec 3, 2002
- National Semiconductor Corporation
- Ronald Pasqualini
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Zero hold time circuit for high speed bus applications
- Patent number 6,397,374
- Issue date May 28, 2002
- National Semiconductor Corporation
- Ronald Pasqualini
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low ground bounce and low power supply bounce output driver with du...
- Patent number 6,380,770
- Issue date Apr 30, 2002
- National Semiconductor Corporation
- Ronald Pasqualini
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low ground bounce and low power supply bounce output driver
- Patent number 6,184,729
- Issue date Feb 6, 2001
- National Semiconductor Corporation
- Ronald Pasqualini
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Universal on-chip initialization circuit
- Patent number 6,160,428
- Issue date Dec 12, 2000
- National Semiconductor Corporation
- Ronald Pasqualini
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low noise electrostatic discharge protection circuit for mixed sign...
- Patent number 6,104,588
- Issue date Aug 15, 2000
- National Semiconductor Corporation
- Dan Ion Hariton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scan flip-flop that holds state during shifting
- Patent number 5,633,606
- Issue date May 27, 1997
- National Semiconductor Corporation
- Brian C. Gaudet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Glitchless clock switching circuit
- Patent number 5,623,223
- Issue date Apr 22, 1997
- National Semiconductor Corporation
- Ronald Pasqualini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bias generator for low ground bounce output driver
- Patent number 5,428,303
- Issue date Jun 27, 1995
- National Semiconductor Corporation
- Ronald Pasqualini
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
High voltage CMOS output buffer constructed from low voltage CMOS t...
- Publication number 20090261865
- Publication date Oct 22, 2009
- RONALD PASQUALINI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PECL/LVPECL input buffer that employs positive feedback to provide...
- Publication number 20090174433
- Publication date Jul 9, 2009
- RONALD PASQUALINI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method of stitching scan flipflops together to form a scan chain wi...
- Publication number 20090174451
- Publication date Jul 9, 2009
- Ronald Pasqualini
- G01 - MEASURING TESTING
Information Patent Application
3-Dimensional method for determining the clock-to-Q delay of a flip...
- Publication number 20090177424
- Publication date Jul 9, 2009
- Ronald Pasqualini
- G01 - MEASURING TESTING
Information Patent Application
ZERO HOLD TIME CIRCUIT FOR HIGH SPEED BUS APPLICATIONS
- Publication number 20020023253
- Publication date Feb 21, 2002
- RONALD PASQUALINI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ESD PROTECTION CIRCUIT UTILIZING FLOATING LATERAL CLAMP DIODES
- Publication number 20010023962
- Publication date Sep 27, 2001
- RONALD PASQUALINI
- H01 - BASIC ELECTRIC ELEMENTS

Ronald Pasqualini

Person

Patents Grantslast 30 patents

Method of stitching scan flipflops together to form a scan chain wi...

ESD structure that protects against power-on and power-off ESD event

High voltage CMOS output buffer constructed from low voltage CMOS t...

Floating diodes

PECL/LVPECL input buffer that employs positive feedback to provide...

Wideband power-on reset circuit

High speed, low power, pipelined zero crossing detector that utiliz...

Wideband power-on reset circuit with glitch-free output

Flipflop that can tolerate arbitrarily slow clock edges

Method and metric for low power standard cell logic synthesis

High speed, universal polarity full adder which consumes minimal po...

Low power, high speed logic controller that implements thermometer-...

High speed synchronizer for simultaneously initializing rising edge...

Gated clock circuit with a substantially increased control signal d...

ESD protection circuit that can tolerate a negative input voltage d...

Low power, minimal area tap multiplier

ESD protection circuit utilizing floating lateral clamp diodes

Integrated circuit package with low inductance ground path and impr...

Electrostatic discharge protection circuit with cascoded trigger-sw...

Flip flop which has complementary, symmetric, minimal timing skew o...

High speed, low power, minimal area double edge triggered flip flop

Zero hold time circuit for high speed bus applications

Low ground bounce and low power supply bounce output driver with du...

Low ground bounce and low power supply bounce output driver

Universal on-chip initialization circuit

Low noise electrostatic discharge protection circuit for mixed sign...

Scan flip-flop that holds state during shifting

Glitchless clock switching circuit

Bias generator for low ground bounce output driver

Patents Applicationslast 30 patents

High voltage CMOS output buffer constructed from low voltage CMOS t...

PECL/LVPECL input buffer that employs positive feedback to provide...

Method of stitching scan flipflops together to form a scan chain wi...

3-Dimensional method for determining the clock-to-Q delay of a flip...

ZERO HOLD TIME CIRCUIT FOR HIGH SPEED BUS APPLICATIONS

ESD PROTECTION CIRCUIT UTILIZING FLOATING LATERAL CLAMP DIODES