Rong-Wu Chien

Person

Chyai, TW

People

Patents Grantslast 30 patents

Information Patent Grant
High contrast, low noise alignment mark for laser trimming of redun...
- Patent number 6,307,273
- Issue date Oct 23, 2001
- Vanguard International Semiconductor Corporation
- Rong-Wu Chien
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method to prevent CMP overpolish
- Patent number 6,204,195
- Issue date Mar 20, 2001
- Vanguard International Semiconductor Corporation
- Rong-Wu Chien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating crown-shaped capacitor structures
- Patent number 6,168,987
- Issue date Jan 2, 2001
- Vanguard International Semiconductor Corp.
- Erik S. Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High stress oxide to eliminate BPSG/SiN cracking
- Patent number 6,136,688
- Issue date Oct 24, 2000
- Vanguard International Semiconductor Corporation
- Keng-Chu Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a monitor pad for chemical mechanical polis...
- Patent number 6,043,160
- Issue date Mar 28, 2000
- Vanguard International Semiconductor Corporation
- Rong-Wu Chien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post chemical mechanical polishing, clean procedure, used for fabri...
- Patent number 6,010,942
- Issue date Jan 4, 2000
- Vanguard International Semiconductor Corporation
- Rong-Wu Chien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for removing fluorinated photoresist layers from semiconduct...
- Patent number 5,904,154
- Issue date May 18, 1999
- Vanguard International Semiconductor Corporation
- Rong-Wu Chien
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of forming contact holes of reduced dimensions by using in-s...
- Patent number 5,895,740
- Issue date Apr 20, 1999
- Vanguard International Semiconductor Corp.
- Rong-Wu Chien
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
High contrast, low noise alignment mark for laser trimming of redun...
- Patent number 5,869,383
- Issue date Feb 9, 1999
- Vanguard International Semiconductor Corporation
- Rong-Wu Chien
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Soft ashing method for removing fluorinated photoresists layers fro...
- Patent number 5,702,869
- Issue date Dec 30, 1997
- Vanguard International Semiconductor Corporation
- Rong-Wu Chien
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for fabricating stacked capacitors in a DRAM cell
- Patent number 5,686,337
- Issue date Nov 11, 1997
- Vanguard International Semiconductor Corporation
- Chao-Ming Koh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming nitride sidewalls having spacer feet in a locos p...
- Patent number 5,643,824
- Issue date Jul 1, 1997
- Vanguard International Semiconductor Corporation
- Rong-Wu Chien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of contact formation and planarization for semiconductor pro...
- Patent number 5,597,764
- Issue date Jan 28, 1997
- Vanguard International Semiconductor Corporation
- Chao-Ming Koh
- H01 - BASIC ELECTRIC ELEMENTS

Rong-Wu Chien

Person

Patents Grantslast 30 patents

High contrast, low noise alignment mark for laser trimming of redun...

Method to prevent CMP overpolish

Method for fabricating crown-shaped capacitor structures

High stress oxide to eliminate BPSG/SiN cracking

Method of manufacturing a monitor pad for chemical mechanical polis...

Post chemical mechanical polishing, clean procedure, used for fabri...

Method for removing fluorinated photoresist layers from semiconduct...

Method of forming contact holes of reduced dimensions by using in-s...

High contrast, low noise alignment mark for laser trimming of redun...

Soft ashing method for removing fluorinated photoresists layers fro...

Method for fabricating stacked capacitors in a DRAM cell

Method of forming nitride sidewalls having spacer feet in a locos p...

Method of contact formation and planarization for semiconductor pro...