Rongchang Yan

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New Kensington, PA, US

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Patents Grantslast 30 patents

Information Patent Grant
Technique for modeling parasitics from layout during circuit design...
- Patent number 8,612,921
- Issue date Dec 17, 2013
- Cadence Design Systems, Inc.
- Prakash Gopalakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for modeling parasitics from layout during circuit design...
- Patent number 8,584,072
- Issue date Nov 12, 2013
- Cadence Design Systems, Inc.
- Prakash Gopalakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for modeling parasitics from layout during circuit design...
- Patent number 8,261,228
- Issue date Sep 4, 2012
- Cadence Design Systems, Inc.
- Prakash Gopalakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for tuning a circuit
- Patent number 7,584,440
- Issue date Sep 1, 2009
- Cadence Design Systems, Inc.
- Rongchang Yan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and system for tuning a circuit
- Publication number 20080104548
- Publication date May 1, 2008
- Cadence Design Systems, Inc.
- Rongchang Yan
- G06 - COMPUTING CALCULATING COUNTING