Ross Donelly

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Simultaneous placement of large and small cells in an electronic ci...
- Patent number 6,983,431
- Issue date Jan 3, 2006
- Synopsys, Inc.
- Ross A. Donelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placing cells of an IC design using partition preconditioning
- Patent number 6,951,003
- Issue date Sep 27, 2005
- Synopsys, Inc.
- Troy W. Barbee, III
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constrained optimization with linear constraints to remove overlap...
- Patent number 6,948,143
- Issue date Sep 20, 2005
- Synopsys, Inc.
- Ross A. Donelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple pass optimization for automatic electronic circuit placement
- Patent number 6,766,500
- Issue date Jul 20, 2004
- Synopsys, Inc.
- Ross A. Donelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-linear optimization system and method for wire length and delay...
- Patent number 6,671,859
- Issue date Dec 30, 2003
- Synopsys, Inc.
- William C. Naylor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quick placement of electronic circuits using orthogonal one dimensi...
- Patent number 6,665,851
- Issue date Dec 16, 2003
- Synopsys, Inc.
- Ross A. Donelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-linear optimization system and method for wire length and densi...
- Patent number 6,662,348
- Issue date Dec 9, 2003
- Synopsys, Inc.
- William C. Naylor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-linear optimization system and method for wire length and delay...
- Patent number 6,301,693
- Issue date Oct 9, 2001
- Synopsys, Inc.
- William C. Naylor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-linear optimization system and method for wire length and densi...
- Patent number 6,282,693
- Issue date Aug 28, 2001
- Synopsys, Inc.
- William C. Naylor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphic representation of circuit analysis for circuit design and t...
- Patent number 6,212,666
- Issue date Apr 3, 2001
- Synopsys, Inc.
- Karl W. Gohl
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Placing cells of an IC design using partition preconditioning
- Publication number 20040230931
- Publication date Nov 18, 2004
- Troy W. Barbee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Simultaneous placement of large and small cells in an electronic ci...
- Publication number 20040225971
- Publication date Nov 11, 2004
- Ross A. Donelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Constrained optimization with linear constraints to remove overlap...
- Publication number 20040225982
- Publication date Nov 11, 2004
- Ross A. Donelly
- G06 - COMPUTING CALCULATING COUNTING

Ross Donelly

Person

Patents Grantslast 30 patents

Simultaneous placement of large and small cells in an electronic ci...

Placing cells of an IC design using partition preconditioning

Constrained optimization with linear constraints to remove overlap...

Multiple pass optimization for automatic electronic circuit placement

Non-linear optimization system and method for wire length and delay...

Quick placement of electronic circuits using orthogonal one dimensi...

Non-linear optimization system and method for wire length and densi...

Non-linear optimization system and method for wire length and delay...

Non-linear optimization system and method for wire length and densi...

Graphic representation of circuit analysis for circuit design and t...

Patents Applicationslast 30 patents

Placing cells of an IC design using partition preconditioning

Simultaneous placement of large and small cells in an electronic ci...

Constrained optimization with linear constraints to remove overlap...