Roy D. Darling

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Forest Grove, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Structure and method for multiplexing pins for in-system programming
- Patent number 5,336,951
- Issue date Aug 9, 1994
- Lattice Semiconductor Corporation
- Gregg R. Josephson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure and method for multiplexing pins for in-system programming
- Patent number 5,237,218
- Issue date Aug 17, 1993
- Lattice Semiconductor Corporation
- Gregg R. Josephson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device configurable input/output cell
- Patent number 4,896,296
- Issue date Jan 23, 1990
- Lattice Semiconductor Corporation
- John E. Turner
- G01 - MEASURING TESTING
Information Patent Grant
In-system programmable logic device
- Patent number 4,879,688
- Issue date Nov 7, 1989
- Lattice Semiconductor Corporation
- John E. Turner
- G01 - MEASURING TESTING
Information Patent Grant
In-system programmable logic device with four dedicated terminals
- Patent number 4,855,954
- Issue date Aug 8, 1989
- Lattice Semiconductor Corporation
- John E. Turner
- G01 - MEASURING TESTING