Ruben Zepeda

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Yorba Linda, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Method for anchoring a conductive cap on a filled via in a printed...
- Patent number 9,913,382
- Issue date Mar 6, 2018
- Viasystems Technologies Corp. L.L.C.
- Rajwant Sidhu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Systems and methods for reducing overhang on electroplated surfaces...
- Patent number 9,017,540
- Issue date Apr 28, 2015
- Viasystems Technologies Corp. L.L.C.
- Rajwant S. Sidhu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Manufacturing methods of multilayer printed circuit board having st...
- Patent number 8,453,322
- Issue date Jun 4, 2013
- DDI Global Corp.
- Raj Kumar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR ANCHORING A CONDUCTIVE CAP ON A FILLED VIA IN A PRINTED...
- Publication number 20160316563
- Publication date Oct 27, 2016
- Viasystems Technologies Corp., L.L.C.
- Rajwant Sidhu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SYSTEMS AND METHODS FOR REDUCING OVERHANG ON ELECTROPLATED SURFACES...
- Publication number 20110308956
- Publication date Dec 22, 2011
- Rajwant S. Sidhu
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
ADDITIONAL FUNCTIONALITY SINGLE LAMINATION STACKED VIA WITH PLATED...
- Publication number 20100038125
- Publication date Feb 18, 2010
- Raj Kumar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR