Rubin Ajit PAREKHJI

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Tests for integrated circuit (IC) chips
- Patent number 11,994,559
- Issue date May 28, 2024
- Texas Instruments Incorporated
- Lakshmanan Balasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compressed scan chain diagnosis by internal chain observation, proc...
- Patent number 11,921,159
- Issue date Mar 5, 2024
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Compressed scan chain diagnosis by internal chain observation, proc...
- Patent number 11,592,483
- Issue date Feb 28, 2023
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Methods of testing multiple dies
- Patent number 11,320,478
- Issue date May 3, 2022
- Texas Instruments Incorporated
- Rubin Ajit Parekhji
- G01 - MEASURING TESTING
Information Patent Grant
Functional circuitry, decompressor circuitry, scan circuitry, maski...
- Patent number 11,119,152
- Issue date Sep 14, 2021
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Dynamically protective scan data control
- Patent number 10,746,797
- Issue date Aug 18, 2020
- Texas Instruments Incorporated
- Rubin Ajit Parekhji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods of testing multiple dies
- Patent number 10,684,322
- Issue date Jun 16, 2020
- Texas Instruments Incorporated
- Rubin Ajit Parekhji
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for optimal trim calibrations in integrated cir...
- Patent number 10,606,723
- Issue date Mar 31, 2020
- Texas Instruments Incorporated
- Pankaj Bongale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compressed scan chains with three input mask gates and registers
- Patent number 10,591,540
- Issue date Mar 17, 2020
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods of testing multiple dies
- Patent number 10,180,454
- Issue date Jan 15, 2019
- Texas Instruments Incorporated
- Rubin Ajit Parekhji
- G01 - MEASURING TESTING
Information Patent Grant
Compressed scan chains with three input mask gates and registers
- Patent number 9,952,283
- Issue date Apr 24, 2018
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit providing different levels of concurrency among radio...
- Patent number 9,581,645
- Issue date Feb 28, 2017
- Texas Instruments Incorporated
- Adesh Sontakke
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for concurrent test of flash memory cores
- Patent number 9,263,147
- Issue date Feb 16, 2016
- Texas Instruments Incorporated
- Rajat Mehrotra
- G11 - INFORMATION STORAGE
Information Patent Grant
Decompressed scan chain masking circuit shift register with log2(n/...
- Patent number 9,229,055
- Issue date Jan 5, 2016
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain masking qualification circuit shift register and bit-fie...
- Patent number 9,091,729
- Issue date Jul 28, 2015
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuits capable of generating test mode control signals...
- Patent number 8,972,807
- Issue date Mar 3, 2015
- Texas Instruments Incorporated
- Rajesh Mittal
- G01 - MEASURING TESTING
Information Patent Grant
Masking circuit removing unknown bit from cell in scan chain
- Patent number 8,887,018
- Issue date Nov 11, 2014
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Scan compression architecture with bypassable scan chains for low t...
- Patent number 8,856,601
- Issue date Oct 7, 2014
- Texas Instruments Incorporated
- Srivaths Ravi
- G01 - MEASURING TESTING
Information Patent Grant
Circuits and methods for dynamic allocation of scan test resources
- Patent number 8,839,063
- Issue date Sep 16, 2014
- Texas Instruments Incorporated
- Rubin Ajit Parekhji
- G01 - MEASURING TESTING
Information Patent Grant
Interruptible non-destructive run-time built-in self-test for field...
- Patent number 8,799,713
- Issue date Aug 5, 2014
- Texas Instruments Incorporated
- Swathi Gangasani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self-test methods, circuits and apparatus for concurrent t...
- Patent number 8,694,276
- Issue date Apr 8, 2014
- Texas Instruments Incorporated
- Adesh Sharadrao Sontakke
- G01 - MEASURING TESTING
Information Patent Grant
Low overhead and timing improved architecture for performing error...
- Patent number 8,671,329
- Issue date Mar 11, 2014
- Texas Instruments Incorporated
- Sanjay Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Low overhead and timing improved architecture for performing error...
- Patent number 8,438,344
- Issue date May 7, 2013
- Texas Instruments Incorporated
- Sanjay Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Structures and control processes for efficient generation of differ...
- Patent number 8,438,437
- Issue date May 7, 2013
- Texas Instruments Incorporated
- Arvind Jain
- G01 - MEASURING TESTING
Information Patent Grant
On-chip seed generation using boolean functions for LFSR re-seeding...
- Patent number 8,286,042
- Issue date Oct 9, 2012
- Texas Instruments Incorporated
- Swathi Gangasani
- G01 - MEASURING TESTING
Information Patent Grant
Enhanced control in scan tests of integrated circuits with partitio...
- Patent number 8,205,125
- Issue date Jun 19, 2012
- Texas Instruments Incorporated
- Alan David Hales
- G01 - MEASURING TESTING
Information Patent Grant
Testing of modules operating with different characteristics of cont...
- Patent number 7,213,184
- Issue date May 1, 2007
- Texas Instruments Incorporated
- Nikila Krishnamoorthy
- G01 - MEASURING TESTING
Information Patent Grant
Generating an abbreviated netlist including pseudopin inputs and ou...
- Patent number 7,203,880
- Issue date Apr 10, 2007
- Texas Instruments Incorporated
- Srinivasa Chakravarthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
At-speed ATPG testing and apparatus for SoC designs having multiple...
- Patent number 7,134,061
- Issue date Nov 7, 2006
- Texas Instruments Incorporated
- Anupama Aniruddha Agashe
- G01 - MEASURING TESTING
Information Patent Grant
Mechanism to enhance observability of integrated circuit failures d...
- Patent number 7,120,842
- Issue date Oct 10, 2006
- Texas Instruments Incorporated
- Gordhan Barevadia
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20230194605
- Publication date Jun 22, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
TESTS FOR INTEGRATED CIRCUIT (IC) CHIPS
- Publication number 20230143500
- Publication date May 11, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lakshmanan Balasubramanian
- G01 - MEASURING TESTING
Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20210364569
- Publication date Nov 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
METHODS OF TESTING MULTIPLE DIES
- Publication number 20200379031
- Publication date Dec 3, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Rubin Ajit PAREKHJI
- G01 - MEASURING TESTING
Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20200174069
- Publication date Jun 4, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
IDENTIFYING DEFECT SENSITIVE CODES FOR TESTING DEVICES WITH INPUT O...
- Publication number 20200057106
- Publication date Feb 20, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Lakshmanan Balasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS OF TESTING MULTIPLE DIES
- Publication number 20190154755
- Publication date May 23, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Rubin Ajit PAREKHJI
- G01 - MEASURING TESTING
Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20180210030
- Publication date Jul 26, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMS AND METHODS FOR OPTIMAL TRIM CALIBRATIONS IN INTEGRATED CIR...
- Publication number 20170177456
- Publication date Jun 22, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Pankaj BONGALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS OF TESTING MULTIPLE DIES
- Publication number 20170153288
- Publication date Jun 1, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Rubin Ajit PAREKHJI
- G01 - MEASURING TESTING
Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20160069958
- Publication date Mar 10, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
SELF-TEST METHODS AND SYSTEMS FOR DIGITAL CIRCUITS
- Publication number 20160003900
- Publication date Jan 7, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR CONCURRENT TEST OF FLASH MEMORY CORES
- Publication number 20150325308
- Publication date Nov 12, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Rajat Mehrotra
- G11 - INFORMATION STORAGE
Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20150285860
- Publication date Oct 8, 2015
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20150006987
- Publication date Jan 1, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
BUILT-IN SELF-TEST METHODS, CIRCUITS AND APPARATUS FOR CONCURRENT T...
- Publication number 20140232422
- Publication date Aug 21, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Adesh Sontakke
- G01 - MEASURING TESTING
Information Patent Application
CIRCUITS AND METHODS FOR DYNAMIC ALLOCATION OF SCAN TEST RESOURCES
- Publication number 20140208177
- Publication date Jul 24, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Rubin Ajit Parekhji
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUITS CAPABLE OF GENERATING TEST MODE CONTROL SIGNALS...
- Publication number 20130305106
- Publication date Nov 14, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Rajesh Mittal
- G01 - MEASURING TESTING
Information Patent Application
LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR...
- Publication number 20130246889
- Publication date Sep 19, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Sanjay Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scan Compression Architecture with Bypassable Scan Chains for Low T...
- Publication number 20130159800
- Publication date Jun 20, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Srivaths Ravi
- G01 - MEASURING TESTING
Information Patent Application
INTERRUPTIBLE NON-DESTRUCTIVE RUN-TIME BUILT-IN SELF-TEST FOR FIELD...
- Publication number 20120226942
- Publication date Sep 6, 2012
- Texas Instruments, Incorporated
- Swathi Gangasani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUILT-IN SELF-TEST METHODS, CIRCUITS AND APPARATUS FOR CONCURRENT T...
- Publication number 20120191400
- Publication date Jul 26, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Adesh Sharadrao Sontakke
- G01 - MEASURING TESTING
Information Patent Application
STRUCTURES AND CONTROL PROCESSES FOR EFFICIENT GENERATION OF DIFFER...
- Publication number 20120030532
- Publication date Feb 2, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Arvind Jain
- G01 - MEASURING TESTING
Information Patent Application
COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...
- Publication number 20110307750
- Publication date Dec 15, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Application
LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR...
- Publication number 20110225475
- Publication date Sep 15, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Sanjay Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIO...
- Publication number 20110099442
- Publication date Apr 28, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Alan David Hales
- G01 - MEASURING TESTING
Information Patent Application
On-Chip Seed Generation Using Boolean Functions for LFSR Re-Seeding...
- Publication number 20100218059
- Publication date Aug 26, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Swathi Gangasani
- G01 - MEASURING TESTING
Information Patent Application
Generating scan test vectors for proprietary cores using pseudo pins
- Publication number 20070288797
- Publication date Dec 13, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasa Chakravarthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Testing of modules operating with different characteristics of cont...
- Publication number 20050091562
- Publication date Apr 28, 2005
- TEXAS INSTRUMENTS INCORPORATED
- Nikila KRISHNAMOORTHY
- G01 - MEASURING TESTING
Information Patent Application
Mechanism to enhance observability of integrated circuit failures d...
- Publication number 20050066243
- Publication date Mar 24, 2005
- Gordhan Barevadia
- G01 - MEASURING TESTING

Rubin Ajit PAREKHJI

Person

Patents Grantslast 30 patents

Tests for integrated circuit (IC) chips

Compressed scan chain diagnosis by internal chain observation, proc...

Compressed scan chain diagnosis by internal chain observation, proc...

Methods of testing multiple dies

Functional circuitry, decompressor circuitry, scan circuitry, maski...

Dynamically protective scan data control

Systems and methods of testing multiple dies

Systems and methods for optimal trim calibrations in integrated cir...

Compressed scan chains with three input mask gates and registers

Systems and methods of testing multiple dies

Compressed scan chains with three input mask gates and registers

Test circuit providing different levels of concurrency among radio...

Method and apparatus for concurrent test of flash memory cores

Decompressed scan chain masking circuit shift register with log2(n/...

Scan chain masking qualification circuit shift register and bit-fie...

Integrated circuits capable of generating test mode control signals...

Masking circuit removing unknown bit from cell in scan chain

Scan compression architecture with bypassable scan chains for low t...

Circuits and methods for dynamic allocation of scan test resources

Interruptible non-destructive run-time built-in self-test for field...

Built-in self-test methods, circuits and apparatus for concurrent t...

Low overhead and timing improved architecture for performing error...

Low overhead and timing improved architecture for performing error...

Structures and control processes for efficient generation of differ...

On-chip seed generation using boolean functions for LFSR re-seeding...

Enhanced control in scan tests of integrated circuits with partitio...

Testing of modules operating with different characteristics of cont...

Generating an abbreviated netlist including pseudopin inputs and ou...

At-speed ATPG testing and apparatus for SoC designs having multiple...

Mechanism to enhance observability of integrated circuit failures d...

Patents Applicationslast 30 patents

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

TESTS FOR INTEGRATED CIRCUIT (IC) CHIPS

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

METHODS OF TESTING MULTIPLE DIES

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

IDENTIFYING DEFECT SENSITIVE CODES FOR TESTING DEVICES WITH INPUT O...

SYSTEMS AND METHODS OF TESTING MULTIPLE DIES

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

SYSTEMS AND METHODS FOR OPTIMAL TRIM CALIBRATIONS IN INTEGRATED CIR...

SYSTEMS AND METHODS OF TESTING MULTIPLE DIES

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

SELF-TEST METHODS AND SYSTEMS FOR DIGITAL CIRCUITS

METHOD AND APPARATUS FOR CONCURRENT TEST OF FLASH MEMORY CORES

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

BUILT-IN SELF-TEST METHODS, CIRCUITS AND APPARATUS FOR CONCURRENT T...

CIRCUITS AND METHODS FOR DYNAMIC ALLOCATION OF SCAN TEST RESOURCES

INTEGRATED CIRCUITS CAPABLE OF GENERATING TEST MODE CONTROL SIGNALS...

LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR...

Scan Compression Architecture with Bypassable Scan Chains for Low T...

INTERRUPTIBLE NON-DESTRUCTIVE RUN-TIME BUILT-IN SELF-TEST FOR FIELD...

BUILT-IN SELF-TEST METHODS, CIRCUITS AND APPARATUS FOR CONCURRENT T...

STRUCTURES AND CONTROL PROCESSES FOR EFFICIENT GENERATION OF DIFFER...

COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROC...

LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR...

ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIO...

On-Chip Seed Generation Using Boolean Functions for LFSR Re-Seeding...

Generating scan test vectors for proprietary cores using pseudo pins

Testing of modules operating with different characteristics of cont...

Mechanism to enhance observability of integrated circuit failures d...