Rui Zhang

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 12,132,002
- Issue date Oct 29, 2024
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 11,694,960
- Issue date Jul 4, 2023
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for an inductor at a first level interface
- Patent number 11,322,290
- Issue date May 3, 2022
- Intel Corporation
- Cheng Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 11,133,257
- Issue date Sep 28, 2021
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for an inductor at a second level interface
- Patent number 11,031,360
- Issue date Jun 8, 2021
- Intel Corporation
- Cheng Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for an inductor at a second level interface
- Patent number 10,777,514
- Issue date Sep 15, 2020
- Intel Corporation
- Cheng Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 10,475,745
- Issue date Nov 12, 2019
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 10,103,103
- Issue date Oct 16, 2018
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 9,640,485
- Issue date May 2, 2017
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge interconnection with layered interconnect structures
- Patent number 9,147,663
- Issue date Sep 29, 2015
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of estimating sampling clock offset, a sampling clock offset...
- Patent number 8,767,855
- Issue date Jul 1, 2014
- Greenvity Communications, Inc.
- Rui Zhang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
MICROMETER METAL PARTICLE REINFORCED TIN-BISMUTH LOW TEMPERATURE SO...
- Publication number 20250128362
- Publication date Apr 24, 2025
- Intel Corporation
- Rui Zhang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
CONTROLLING SUBSTRATE BUMP HEIGHT
- Publication number 20250112164
- Publication date Apr 3, 2025
- Intel Corporation
- Bohan SHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GLASS CORES INCLUDING PROTRUDING THROUGH GLASS VIAS AND RELATED MET...
- Publication number 20250105074
- Publication date Mar 27, 2025
- Intel Corporation
- Bohan Shan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20250015004
- Publication date Jan 9, 2025
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20240014138
- Publication date Jan 11, 2024
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLDER GRID ARRAY FOR ATTACHMENT OF A DIE PACKAGE
- Publication number 20230197659
- Publication date Jun 22, 2023
- Intel Corporation
- Mukund Ayalasomayajula
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR AN INDUCTOR AT A FIRST LEVEL INTERFACE
- Publication number 20220230800
- Publication date Jul 21, 2022
- Intel Corporation
- Cheng Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20210384129
- Publication date Dec 9, 2021
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR AN INDUCTOR AT A SECOND LEVEL INTERFACE
- Publication number 20200373257
- Publication date Nov 26, 2020
- Intel Corporation
- Cheng Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20200043852
- Publication date Feb 6, 2020
- Intel Corporation
- Yueli Liu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
TECHNIQUES FOR AN INDUCTOR AT A FIRST LEVEL INTERFACE
- Publication number 20190385780
- Publication date Dec 19, 2019
- Intel Corporation
- Cheng Xu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNIQUES FOR AN INDUCTOR AT A SECOND LEVEL INTERFACE
- Publication number 20190385959
- Publication date Dec 19, 2019
- Intel Corporation
- Cheng Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20190013271
- Publication date Jan 10, 2019
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20170207168
- Publication date Jul 20, 2017
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20150364423
- Publication date Dec 17, 2015
- Intel Corporation
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES
- Publication number 20140353827
- Publication date Dec 4, 2014
- Yueli Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF ESTIMATING SAMPLING CLOCK OFFSET, A SAMPLING CLOCK OFFSET...
- Publication number 20130266056
- Publication date Oct 10, 2013
- Greenvity Communications, Inc.
- Rui Zhang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Person

Patents Grantslast 30 patents

Bridge interconnection with layered interconnect structures

Bridge interconnection with layered interconnect structures

Techniques for an inductor at a first level interface

Bridge interconnection with layered interconnect structures

Techniques for an inductor at a second level interface

Techniques for an inductor at a second level interface

Bridge interconnection with layered interconnect structures

Bridge interconnection with layered interconnect structures

Bridge interconnection with layered interconnect structures

Bridge interconnection with layered interconnect structures

Method of estimating sampling clock offset, a sampling clock offset...

Patents Applicationslast 30 patents

MICROMETER METAL PARTICLE REINFORCED TIN-BISMUTH LOW TEMPERATURE SO...

CONTROLLING SUBSTRATE BUMP HEIGHT

GLASS CORES INCLUDING PROTRUDING THROUGH GLASS VIAS AND RELATED MET...

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

SOLDER GRID ARRAY FOR ATTACHMENT OF A DIE PACKAGE

TECHNIQUES FOR AN INDUCTOR AT A FIRST LEVEL INTERFACE

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

TECHNIQUES FOR AN INDUCTOR AT A SECOND LEVEL INTERFACE

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

TECHNIQUES FOR AN INDUCTOR AT A FIRST LEVEL INTERFACE

TECHNIQUES FOR AN INDUCTOR AT A SECOND LEVEL INTERFACE

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES

METHOD OF ESTIMATING SAMPLING CLOCK OFFSET, A SAMPLING CLOCK OFFSET...