Runsheng Wang

Person

Beijing, CN

People

Patents Grantslast 30 patents

Information Patent Grant
Method of bias temperature instability calculation and prediction f...
- Patent number 10,621,386
- Issue date Apr 14, 2020
- Cadence Design Systems, Inc.
- Alvin Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for fabricating FinFET with separated double gates on bulk s...
- Patent number 9,478,641
- Issue date Oct 25, 2016
- Peking University
- Ru Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable array of silicon nanowire field effect transistor and...
- Patent number 9,099,500
- Issue date Aug 4, 2015
- Peking University
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method for fabricating silicon nanowire field effect transistor bas...
- Patent number 9,034,702
- Issue date May 19, 2015
- Peking University
- Ru Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for testing density and location of gate dielectric layer tr...
- Patent number 9,018,968
- Issue date Apr 28, 2015
- Peking University
- Ru Huang
- G01 - MEASURING TESTING
Information Patent Grant
Field effect transistor with a vertical channel and fabrication met...
- Patent number 8,901,644
- Issue date Dec 2, 2014
- Peking University
- Ru Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for testing trap density of gate dielectric layer in semicon...
- Patent number 8,866,507
- Issue date Oct 21, 2014
- Peking University
- Ru Huang
- G01 - MEASURING TESTING
Information Patent Grant
Method for fabricating semiconductor nano circular ring
- Patent number 8,722,312
- Issue date May 13, 2014
- Peking University
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Fabrication method of vertical silicon nanowire field effect transi...
- Patent number 8,592,276
- Issue date Nov 26, 2013
- Peking University
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Grant
High voltage-resistant lateral double-diffused transistor based on...
- Patent number 8,564,031
- Issue date Oct 22, 2013
- Peking University
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method for fabricating surrounding-gate silicon nanowire transistor...
- Patent number 8,563,370
- Issue date Oct 22, 2013
- Peking University
- Ru Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication method for surrounding gate silicon nanowire transistor...
- Patent number 8,513,067
- Issue date Aug 20, 2013
- Peking University
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method for fabricating ultra-fine nanowire
- Patent number 8,372,752
- Issue date Feb 12, 2013
- Peking University
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method for fabricating a tunneling field-effect transistor
- Patent number 8,288,238
- Issue date Oct 16, 2012
- Peking University
- Ru Huang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method for establishing transistor statistical model based on artif...
- Publication number 20240273274
- Publication date Aug 15, 2024
- PEKING UNIVERSITY SHENZHEN GRADUATE SCHOOL
- Lining ZHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR EXTRACTING TRAP TIME CONSTANT OF GATE DIELECTRIC LAYER I...
- Publication number 20160153923
- Publication date Jun 2, 2016
- Peking University
- Ru HUANG
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR FABRICATING FINFET WITH SEPARATED DOUBLE GATES ON BULK S...
- Publication number 20150236130
- Publication date Aug 20, 2015
- Peking University
- Ru Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING FINFET ON GERMANIUM OR GROUP III-V SEMICONDU...
- Publication number 20150140758
- Publication date May 21, 2015
- Peking University
- Ru Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR TESTING DENSITY AND LOCATION OF GATE DIELECTRIC LAYER TR...
- Publication number 20130214810
- Publication date Aug 22, 2013
- Peking University
- Ru Huang
- G01 - MEASURING TESTING
Information Patent Application
FIELD EFFECT TRANSISTOR WITH A VERTICAL CHANNEL AND FABRICATION MET...
- Publication number 20130168759
- Publication date Jul 4, 2013
- Peking University
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD FOR FABRICATING ULTRA-FINE NANOWIRE
- Publication number 20130130503
- Publication date May 23, 2013
- Peking University
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Application
PROGRAMMABLE ARRAY OF SILICON NANOWIRE FIELD EFFECT TRANSISTOR AND...
- Publication number 20130075701
- Publication date Mar 28, 2013
- Peking University
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Application
FABRICATION METHOD FOR SURROUNDING GATE SILICON NANOWIRE TRANSISTOR...
- Publication number 20130017654
- Publication date Jan 17, 2013
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Application
FABRICATION METHOD OF VERTICAL SILICON NANOWIRE FIELD EFFECT TRANSI...
- Publication number 20130011980
- Publication date Jan 10, 2013
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD FOR FABRICATING SURROUNDING-GATE SILICON NANOWIRE TRANSISTOR...
- Publication number 20120302014
- Publication date Nov 29, 2012
- Peking University
- Ru Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Fabricating Silicon Nanowire Field Effect Transistor Bas...
- Publication number 20120302027
- Publication date Nov 29, 2012
- Ru Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SURFACE TREATMENT METHOD FOR GERMANIUM BASED DEVICE
- Publication number 20120264311
- Publication date Oct 18, 2012
- Peking University
- Xia An
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
METHOD FOR FABRICATING FINE LINE
- Publication number 20120238097
- Publication date Sep 20, 2012
- Peking University
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Application
HIGH VOLTAGE-RESISTANT LATERAL DOUBLE-DIFFUSED TRANSISTOR BASED ON...
- Publication number 20120199808
- Publication date Aug 9, 2012
- Peking University
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD FOR FABRICATING SEMICONDUCTOR NANO CIRCULAR RING
- Publication number 20120190202
- Publication date Jul 26, 2012
- Peking University
- Ru Huang
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD FOR TESTING TRAP DENSITY OF GATE DIELECTRIC LAYER IN SEMICON...
- Publication number 20120187976
- Publication date Jul 26, 2012
- Peking University
- Ru Huang
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR FABRICATING A TUNNELING FIELD-EFFECT TRANSISTOR
- Publication number 20120115297
- Publication date May 10, 2012
- Peking University
- Ru Huang
- H01 - BASIC ELECTRIC ELEMENTS

Runsheng Wang

Person

Patents Grantslast 30 patents

Method of bias temperature instability calculation and prediction f...

Method for fabricating FinFET with separated double gates on bulk s...

Programmable array of silicon nanowire field effect transistor and...

Method for fabricating silicon nanowire field effect transistor bas...

Method for testing density and location of gate dielectric layer tr...

Field effect transistor with a vertical channel and fabrication met...

Method for testing trap density of gate dielectric layer in semicon...

Method for fabricating semiconductor nano circular ring

Fabrication method of vertical silicon nanowire field effect transi...

High voltage-resistant lateral double-diffused transistor based on...

Method for fabricating surrounding-gate silicon nanowire transistor...

Fabrication method for surrounding gate silicon nanowire transistor...

Method for fabricating ultra-fine nanowire

Method for fabricating a tunneling field-effect transistor

Patents Applicationslast 30 patents

Method for establishing transistor statistical model based on artif...

METHOD FOR EXTRACTING TRAP TIME CONSTANT OF GATE DIELECTRIC LAYER I...

METHOD FOR FABRICATING FINFET WITH SEPARATED DOUBLE GATES ON BULK S...

METHOD FOR FABRICATING FINFET ON GERMANIUM OR GROUP III-V SEMICONDU...

METHOD FOR TESTING DENSITY AND LOCATION OF GATE DIELECTRIC LAYER TR...

FIELD EFFECT TRANSISTOR WITH A VERTICAL CHANNEL AND FABRICATION MET...

METHOD FOR FABRICATING ULTRA-FINE NANOWIRE

PROGRAMMABLE ARRAY OF SILICON NANOWIRE FIELD EFFECT TRANSISTOR AND...

FABRICATION METHOD FOR SURROUNDING GATE SILICON NANOWIRE TRANSISTOR...

FABRICATION METHOD OF VERTICAL SILICON NANOWIRE FIELD EFFECT TRANSI...

METHOD FOR FABRICATING SURROUNDING-GATE SILICON NANOWIRE TRANSISTOR...

Method for Fabricating Silicon Nanowire Field Effect Transistor Bas...

SURFACE TREATMENT METHOD FOR GERMANIUM BASED DEVICE

METHOD FOR FABRICATING FINE LINE

HIGH VOLTAGE-RESISTANT LATERAL DOUBLE-DIFFUSED TRANSISTOR BASED ON...

METHOD FOR FABRICATING SEMICONDUCTOR NANO CIRCULAR RING

METHOD FOR TESTING TRAP DENSITY OF GATE DIELECTRIC LAYER IN SEMICON...

METHOD FOR FABRICATING A TUNNELING FIELD-EFFECT TRANSISTOR