Runzi Chang

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Electronic fuse (eFuse) designs for enhanced chip security
- Patent number 12,046,553
- Issue date Jul 23, 2024
- MARVELL ASIA PTE. LTD.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate stack for metal gate transistor
- Patent number 11,862,453
- Issue date Jan 2, 2024
- Marvell Asia Pte, Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Real-time, in-situ reliability monitoring in an integrated circuit
- Patent number 11,774,490
- Issue date Oct 3, 2023
- MARVELL ASIA PTE. LTD.
- Runzi Chang
- G01 - MEASURING TESTING
Information Patent Grant
Device having bipolar junction transistors and finFET transistors o...
- Patent number 11,721,691
- Issue date Aug 8, 2023
- MARVELL ASIA PTE. LTD.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for configuring a central processing unit havin...
- Patent number 11,630,750
- Issue date Apr 18, 2023
- Marvell Asia Pte, Ltd.
- Runzi Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electrical performance and reliability of a semiconductor device co...
- Patent number 11,527,625
- Issue date Dec 13, 2022
- MARVELL ASIA PTE. LTD.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Decoupling capacitor integrated in system on chip (SOC) device
- Patent number 11,469,295
- Issue date Oct 11, 2022
- MARVELL ASIA PTE. LTD.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Through-silicon via for high-speed interconnects
- Patent number 11,398,431
- Issue date Jul 26, 2022
- MARVELL ASIA PTE. LTD.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mobile storage system for storing and transferring data generated b...
- Patent number 11,134,135
- Issue date Sep 28, 2021
- Marvell Asia Pte, Ltd.
- Runzi Chang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Creating an aligned via and metal line in an integrated circuit inc...
- Patent number 11,081,387
- Issue date Aug 3, 2021
- Marvell Asia Pte, Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for forming finFET analog designs having a modu...
- Patent number 10,978,592
- Issue date Apr 13, 2021
- Marvell Asia Pte., Ltd.
- Hui Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and methods for temperature-based memory management
- Patent number 10,928,870
- Issue date Feb 23, 2021
- Marvell Asia PTE, Ltd.
- Runzi Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for packaging an integrated circuit
- Patent number 10,896,900
- Issue date Jan 19, 2021
- Marvell Asia Pte, Ltd.
- Runzi Chang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Methods and apparatus for fabricating IC chips with tilted patterning
- Patent number 10,854,455
- Issue date Dec 1, 2020
- Marvell Asia Pte, Ltd.
- Runzi Chang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Sub-device field-effect transistor architecture for integrated circ...
- Patent number 10,784,250
- Issue date Sep 22, 2020
- Marvell Asia Pte, Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation components for transistors formed on fin features of semi...
- Patent number 10,784,167
- Issue date Sep 22, 2020
- Marvell Asia Pte, Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Photolithography mask design-rule check assistance
- Patent number 10,713,411
- Issue date Jul 14, 2020
- Marvell Asia Pte, Ltd.
- Runzi Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MRAM structure for efficient manufacturability
- Patent number 10,707,411
- Issue date Jul 7, 2020
- Marvell International Ltd.
- Zining Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory chip design for manufacturing
- Patent number 10,672,861
- Issue date Jun 2, 2020
- Marvell International Ltd.
- Runzi Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fabricating memory devices with optimized gate oxide thickness
- Patent number 10,600,793
- Issue date Mar 24, 2020
- Marvell World Trade Ltd.
- Runzi Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Modular memory-like layout for finFET analog designs
- Patent number 10,535,774
- Issue date Jan 14, 2020
- Marvell International Ltd.
- Hui Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of creating aligned vias in ultra-high density integrated ci...
- Patent number 10,522,394
- Issue date Dec 31, 2019
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and systems for packaging semiconductor devices to improve...
- Patent number 10,431,574
- Issue date Oct 1, 2019
- Marvell World Trade Ltd.
- Runzi Chang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Fabricating memory devices with optimized gate oxide thickness
- Patent number 10,319,727
- Issue date Jun 11, 2019
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation components for transistors formed on fin features of semi...
- Patent number 10,217,669
- Issue date Feb 26, 2019
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and systems to improve yield in multiple chips integration...
- Patent number 10,056,363
- Issue date Aug 21, 2018
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit manufacturing process for aligning threshold vol...
- Patent number 10,037,400
- Issue date Jul 31, 2018
- Marvell World Trade Ltd.
- Runzi Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Package assembly including a semiconductor substrate in which a fir...
- Patent number 9,768,144
- Issue date Sep 19, 2017
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Resistive random access memory cell structure
- Patent number 9,490,427
- Issue date Nov 8, 2016
- Marvell World Trade Ltd.
- Pantas Sutardja
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for mitigating effects of parasitic capacitanc...
- Patent number 9,397,218
- Issue date Jul 19, 2016
- Marvell World Trade Ltd.
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Reducing warpage in a package of stacked integrated circuit dies
- Publication number 20250029948
- Publication date Jan 23, 2025
- Marvell Asia Pte Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE STACK FOR METAL GATE TRANSISTOR
- Publication number 20240088235
- Publication date Mar 14, 2024
- Marvell Asia Pte, Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Gate All-Around (GAA) Field Effect Transistors (FETS) Formed on Bot...
- Publication number 20240072070
- Publication date Feb 29, 2024
- Marvell Asia Pte Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC FUSE (EFUSE) DESIGNS FOR ENHANCED CHIP SECURITY
- Publication number 20230139634
- Publication date May 4, 2023
- Marvell Asia Pte Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Double seal ring and electrical connection of multiple chiplets
- Publication number 20230029110
- Publication date Jan 26, 2023
- Marvell Asia Pte Ltd.
- Lijuan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Three-Dimensional Integration of Processing Chiplet and Static Rand...
- Publication number 20220384408
- Publication date Dec 1, 2022
- Marvell Asia Pte Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Performance of magnetic channel junctions
- Publication number 20220238147
- Publication date Jul 28, 2022
- Marvell Asia Pte Ltd.
- Peng Zhang
- G11 - INFORMATION STORAGE
Information Patent Application
GATE STACK FOR METAL GATE TRANSISTOR
- Publication number 20220069091
- Publication date Mar 3, 2022
- Marvell Asia Pte, Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrical performance of bipolar junction transistors
- Publication number 20210296309
- Publication date Sep 23, 2021
- Marvell Asia Pte Ltd
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Through-Silicon Via for High-Speed Interconnects
- Publication number 20210233853
- Publication date Jul 29, 2021
- Marvell Asia Pte Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CREATING AN ALIGNED VIA AND METAL LINE IN AN INTEGRATED CIRCUIT INC...
- Publication number 20200118868
- Publication date Apr 16, 2020
- Marvell World Trade Ltd.
- Runzi CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sub-Device Field-Effect Transistor Architecture for Integrated Circ...
- Publication number 20200066706
- Publication date Feb 27, 2020
- Marvell World Trade Ltd.
- Runzi Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND SYSTEMS FOR PACKAGING AN INTEGRATED CIRCUIT
- Publication number 20200013768
- Publication date Jan 9, 2020
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apparatus and Methods for Temperature-Based Memory Management
- Publication number 20190369685
- Publication date Dec 5, 2019
- Marvell World Trade Ltd.
- Runzi Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fabricating Memory Devices with Optimized Gate Oxide Thickness
- Publication number 20190259768
- Publication date Aug 22, 2019
- Marvell World Trade Ltd.
- Runzi Chang
- G11 - INFORMATION STORAGE
Information Patent Application
Isolation Components for Transistors Formed on Fin Features of Semi...
- Publication number 20190148236
- Publication date May 16, 2019
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF CREATING ALIGNED VIAS IN ULTRA-HIGH DENSITY INTEGRATED CI...
- Publication number 20190096756
- Publication date Mar 28, 2019
- Marvell World Trade Ltd.
- Runzi CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND SYSTEMS FOR PACKAGING SEMICONDUCTOR DEVICES TO IMPROVE...
- Publication number 20180331088
- Publication date Nov 15, 2018
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and Apparatus for Fabricating IC Chips with Tilted Patterning
- Publication number 20180144941
- Publication date May 24, 2018
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fabricating Memory Devices with Optimized Gate Oxide Thickness
- Publication number 20180122815
- Publication date May 3, 2018
- Marvell World Trade Ltd.
- Runzi Chang
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT MANUFACTURING PROCESS FOR ALIGNING THRESHOLD VOL...
- Publication number 20170351802
- Publication date Dec 7, 2017
- Marvell World Trade Ltd.
- Runzi Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and systems to improve yield in multiple chips integration...
- Publication number 20170133358
- Publication date May 11, 2017
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEMS AND METHODS FOR INCREASING PACKING DENSITY IN A SEMICONDUCT...
- Publication number 20160358909
- Publication date Dec 8, 2016
- Marvell World Trade Ltd.
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMI...
- Publication number 20160329249
- Publication date Nov 10, 2016
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE IN WHICH A FIR...
- Publication number 20160155732
- Publication date Jun 2, 2016
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RESISTIVE RANDOM ACCESS MEMORY CELL STRUCTURE
- Publication number 20160087201
- Publication date Mar 24, 2016
- Marvell World Trade Ltd.
- Pantas Sutardja
- G11 - INFORMATION STORAGE
Information Patent Application
RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES
- Publication number 20150279806
- Publication date Oct 1, 2015
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR MITIGATING EFFECTS OF PARASITIC CAPACITANC...
- Publication number 20150194518
- Publication date Jul 9, 2015
- Marvell World Trade Ltd.
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RESISTIVE RANDOM ACCESS MEMORY CELL STRUCTURE WITH REDUCED PROGRAMM...
- Publication number 20150124520
- Publication date May 7, 2015
- Marvell World Trade Ltd.
- Pantas Sutardja
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR REFORMING A MEMORY CELL OF A MEMORY
- Publication number 20150063004
- Publication date Mar 5, 2015
- Marvell World Trade Ltd.
- Pantas Sutardja
- G11 - INFORMATION STORAGE

Runzi Chang

Person

Patents Grantslast 30 patents

Electronic fuse (eFuse) designs for enhanced chip security

Gate stack for metal gate transistor

Real-time, in-situ reliability monitoring in an integrated circuit

Device having bipolar junction transistors and finFET transistors o...

Systems and methods for configuring a central processing unit havin...

Electrical performance and reliability of a semiconductor device co...

Decoupling capacitor integrated in system on chip (SOC) device

Through-silicon via for high-speed interconnects

Mobile storage system for storing and transferring data generated b...

Creating an aligned via and metal line in an integrated circuit inc...

Systems and methods for forming finFET analog designs having a modu...

Apparatus and methods for temperature-based memory management

Methods and systems for packaging an integrated circuit

Methods and apparatus for fabricating IC chips with tilted patterning

Sub-device field-effect transistor architecture for integrated circ...

Isolation components for transistors formed on fin features of semi...

Photolithography mask design-rule check assistance

MRAM structure for efficient manufacturability

Memory chip design for manufacturing

Fabricating memory devices with optimized gate oxide thickness

Modular memory-like layout for finFET analog designs

Method of creating aligned vias in ultra-high density integrated ci...

Methods and systems for packaging semiconductor devices to improve...

Fabricating memory devices with optimized gate oxide thickness

Isolation components for transistors formed on fin features of semi...

Methods and systems to improve yield in multiple chips integration...

Integrated circuit manufacturing process for aligning threshold vol...

Package assembly including a semiconductor substrate in which a fir...

Resistive random access memory cell structure

Method and apparatus for mitigating effects of parasitic capacitanc...

Patents Applicationslast 30 patents

Reducing warpage in a package of stacked integrated circuit dies

GATE STACK FOR METAL GATE TRANSISTOR

Gate All-Around (GAA) Field Effect Transistors (FETS) Formed on Bot...

ELECTRONIC FUSE (EFUSE) DESIGNS FOR ENHANCED CHIP SECURITY

Double seal ring and electrical connection of multiple chiplets

Three-Dimensional Integration of Processing Chiplet and Static Rand...

Performance of magnetic channel junctions

GATE STACK FOR METAL GATE TRANSISTOR

Electrical performance of bipolar junction transistors

Through-Silicon Via for High-Speed Interconnects

CREATING AN ALIGNED VIA AND METAL LINE IN AN INTEGRATED CIRCUIT INC...

Sub-Device Field-Effect Transistor Architecture for Integrated Circ...

METHODS AND SYSTEMS FOR PACKAGING AN INTEGRATED CIRCUIT

Apparatus and Methods for Temperature-Based Memory Management

Fabricating Memory Devices with Optimized Gate Oxide Thickness

Isolation Components for Transistors Formed on Fin Features of Semi...

METHOD OF CREATING ALIGNED VIAS IN ULTRA-HIGH DENSITY INTEGRATED CI...

METHODS AND SYSTEMS FOR PACKAGING SEMICONDUCTOR DEVICES TO IMPROVE...

Methods and Apparatus for Fabricating IC Chips with Tilted Patterning

Fabricating Memory Devices with Optimized Gate Oxide Thickness

INTEGRATED CIRCUIT MANUFACTURING PROCESS FOR ALIGNING THRESHOLD VOL...

Methods and systems to improve yield in multiple chips integration...

SYSTEMS AND METHODS FOR INCREASING PACKING DENSITY IN A SEMICONDUCT...

ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMI...

PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE IN WHICH A FIR...

RESISTIVE RANDOM ACCESS MEMORY CELL STRUCTURE

RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES

METHOD AND APPARATUS FOR MITIGATING EFFECTS OF PARASITIC CAPACITANC...

RESISTIVE RANDOM ACCESS MEMORY CELL STRUCTURE WITH REDUCED PROGRAMM...

METHOD AND APPARATUS FOR REFORMING A MEMORY CELL OF A MEMORY