Ruth A. Brain

Person

Garthersburg, MD, US

People

Patents Grantslast 30 patents

Information Patent Grant
Metal space centered standard cell architecture to enable higher ce...
- Patent number 11,764,219
- Issue date Sep 19, 2023
- Intel Corporation
- Harshitha Vishwanath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Replacement metal COB integration process for embedded DRAM
- Patent number 11,723,188
- Issue date Aug 8, 2023
- Intel Corporation
- Uygar Avci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via contact patterning method to increase edge placement error margin
- Patent number 11,652,045
- Issue date May 16, 2023
- Intel Corporation
- Mohit K. Haran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive cap-based approaches for conductive via fabrication and...
- Patent number 11,417,567
- Issue date Aug 16, 2022
- Intel Corporation
- Florian Gstrein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ferroelectric-capacitor integration using novel multi-metal-level i...
- Patent number 11,322,504
- Issue date May 3, 2022
- Intel Corporation
- Uygar Avci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via contact patterning method to increase edge placement error margin
- Patent number 11,211,324
- Issue date Dec 28, 2021
- Intel Corporation
- Mohit K. Haran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plug and trench architectures for integrated circuits and methods o...
- Patent number 11,171,043
- Issue date Nov 9, 2021
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive via and metal line end fabrication and structures result...
- Patent number 11,145,541
- Issue date Oct 12, 2021
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power shared cell architecture
- Patent number 11,068,640
- Issue date Jul 20, 2021
- Intel Corporation
- Ranjith Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Etch-stop layer topography for advanced integrated circuit structur...
- Patent number 10,943,817
- Issue date Mar 9, 2021
- Intel Corporation
- Andrew W. Yeoh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Decoupled via fill
- Patent number 10,903,114
- Issue date Jan 26, 2021
- Intel Corporation
- Yuriy V. Shusterman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for forming logic including integrated spin-transfer tor...
- Patent number 10,811,595
- Issue date Oct 20, 2020
- Intel Corporation
- Kevin J. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch-stop layer topography for advanced integrated circuit structur...
- Patent number 10,796,951
- Issue date Oct 6, 2020
- Intel Corporation
- Andrew W. Yeoh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via blocking layer
- Patent number 10,672,650
- Issue date Jun 2, 2020
- Intel Corporation
- Rami Hourani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
AVD hardmask for damascene patterning
- Patent number 10,593,626
- Issue date Mar 17, 2020
- Intel Corporation
- Ruth A. Brain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via blocking layer
- Patent number 10,535,601
- Issue date Jan 14, 2020
- Intel Corporation
- Rami Hourani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Decoupled via fill
- Patent number 10,468,298
- Issue date Nov 5, 2019
- Intel Corporation
- Yuriy V. Shusterman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Decoupled via fill
- Patent number 10,211,098
- Issue date Feb 19, 2019
- Intel Corporation
- Yuriy V. Shusterman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etchstop layers and capacitors
- Patent number 10,032,857
- Issue date Jul 24, 2018
- Intel Corporation
- Ruth A. Brain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure to contact tight pitch conductive layers with...
- Patent number 10,032,643
- Issue date Jul 24, 2018
- Intel Corporation
- Jasmeet S. Chawla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Decoupled via fill
- Patent number 10,026,649
- Issue date Jul 17, 2018
- Intel Corporation
- Yuriy V. Shusterman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via blocking layer
- Patent number 9,899,255
- Issue date Feb 20, 2018
- Intel Corporation
- Rami Hourani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
AVD hardmask for damascene patterning
- Patent number 9,780,038
- Issue date Oct 3, 2017
- Intel Corporation
- Ruth A. Brain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etchstop layers and capacitors
- Patent number 9,607,992
- Issue date Mar 28, 2017
- Intel Corporation
- Ruth A. Brain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
AVD hardmask for damascene patterning
- Patent number 9,502,281
- Issue date Nov 22, 2016
- Intel Corporation
- Ruth A. Brain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etchstop layers and capacitors
- Patent number 9,343,524
- Issue date May 17, 2016
- Intel Corporation
- Ruth A. Brain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Etchstop layers and capacitors
- Patent number 9,054,068
- Issue date Jun 9, 2015
- Intel Corporation
- Ruth A. Brain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Landing structure for through-silicon via
- Patent number 8,933,564
- Issue date Jan 13, 2015
- Intel Corporation
- Christopher M. Pelto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of interconnects in a low-k interlayer dielectrics
- Patent number 8,143,159
- Issue date Mar 27, 2012
- Intel Corporation
- Sean King
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Winged vias to increase overlay margin
- Patent number 8,058,177
- Issue date Nov 15, 2011
- Intel Corporation
- Martin Weiss
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CELL ROWS WITH MIXED HEIGHTS AND MIXED NANORIBBON WIDTHS
- Publication number 20250006721
- Publication date Jan 2, 2025
- Intel Corporation
- Sukru Yemenicioglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLUG & TRENCH ARCHITECTURES FOR INTEGRATED CIRCUITS & METHODS OF MA...
- Publication number 20220068707
- Publication date Mar 3, 2022
- Intel Corporation
- Charles H. WALLACE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA CONTACT PATTERNING METHOD TO INCREASE EDGE PLACEMENT ERROR MARGIN
- Publication number 20220051975
- Publication date Feb 17, 2022
- Intel Corporation
- Mohit K. Haran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LINE PATTERNING IN INTEGRATED CIRCUIT DEVICES
- Publication number 20210183761
- Publication date Jun 17, 2021
- Intel Corporation
- Reken Patel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL SPACE CENTERED STANDARD CELL ARCHITECTURE TO ENABLE HIGHER CE...
- Publication number 20210167066
- Publication date Jun 3, 2021
- Intel Corporation
- Harshitha VISHWANATH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA CONTACT PATTERNING METHOD TO INCREASE EDGE PLACEMENT ERROR MARGIN
- Publication number 20210082805
- Publication date Mar 18, 2021
- Intel Corporation
- Mohit K. Haran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER SHARED CELL ARCHITECTURE
- Publication number 20200279069
- Publication date Sep 3, 2020
- Intel Corporation
- Ranjith KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONDUCTIVE VIA AND METAL LINE END FABRICATION AND STRUCTURES RESULT...
- Publication number 20200185271
- Publication date Jun 11, 2020
- Intel Corporation
- Charles H. WALLACE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DECOUPLED VIA FILL
- Publication number 20200090992
- Publication date Mar 19, 2020
- Intel Corporation
- YURIY V. SHUSTERMAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH-STOP LAYER TOPOGRAPHY FOR ADVANCED INTEGRATED CIRCUIT STRUCTUR...
- Publication number 20200027781
- Publication date Jan 23, 2020
- Intel Corporation
- Andrew W. YEOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REPLACEMENT METAL COB INTEGRATION PROCESS FOR EMBEDDED DRAM
- Publication number 20200006346
- Publication date Jan 2, 2020
- Uygar AVCI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FERROELECTRIC-CAPACITOR INTEGRATION USING NOVEL MULTI-METAL-LEVEL I...
- Publication number 20200006352
- Publication date Jan 2, 2020
- Uygar AVCI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE CAP-BASED APPROACHES FOR CONDUCTIVE VIA FABRICATION AND...
- Publication number 20190363008
- Publication date Nov 28, 2019
- Intel Corporation
- Florian GSTREIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DECOUPLED VIA FILL
- Publication number 20190221478
- Publication date Jul 18, 2019
- Intel Corporation
- YURIY V. SHUSTERMAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLUG & TRENCH ARCHITECTURES FOR INTEGRATED CIRCUITS & METHODS OF MA...
- Publication number 20190206728
- Publication date Jul 4, 2019
- Intel Corporation
- Charles H. WALLACE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH-STOP LAYER TOPOGRAPHY FOR ADVANCED INTEGRATED CIRCUIT STRUCTUR...
- Publication number 20190164818
- Publication date May 30, 2019
- Intel Corporation
- Andrew W. YEOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA BLOCKING LAYER
- Publication number 20190122982
- Publication date Apr 25, 2019
- Intel Corporation
- Rami Hourani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR FORMING LOGIC INCLUDING INTEGRATED SPIN-TRANSFER TOR...
- Publication number 20190081233
- Publication date Mar 14, 2019
- Intel Corporation
- KEVIN J. LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPROACHES FOR INTEGRATING STT-MRAM MEMORY ARRAYS INTO A LOGIC PROC...
- Publication number 20190013353
- Publication date Jan 10, 2019
- Intel Corporation
- Kevin J. LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DECOUPLED VIA FILL
- Publication number 20180350672
- Publication date Dec 6, 2018
- Intel Corporation
- YURIY V. SHUSTERMAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA BLOCKING LAYER
- Publication number 20180174893
- Publication date Jun 21, 2018
- Intel Corporation
- RAMI HOURANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AVD HARDMASK FOR DAMASCENE PATTERNING
- Publication number 20180122744
- Publication date May 3, 2018
- Intel Corporation
- Ruth A. Brain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DECOUPLED VIA FILL
- Publication number 20170338148
- Publication date Nov 23, 2017
- Intel Corporation
- YURIY V. SHUSTERMAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE TO CONTACT TIGHT PITCH CONDUCTIVE LAYERS WITH...
- Publication number 20170330761
- Publication date Nov 16, 2017
- Intel Corporation
- Jasmeet S. CHAWLA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA BLOCKING LAYER
- Publication number 20170330794
- Publication date Nov 16, 2017
- Intel Corporation
- RAMI HOURANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCHSTOP LAYERS AND CAPACITORS
- Publication number 20170148867
- Publication date May 25, 2017
- Intel Corporation
- RUTH A. BRAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AVD HARDMASK FOR DAMASCENE PATTERNING
- Publication number 20170040263
- Publication date Feb 9, 2017
- Intel Corporation
- Ruth A. Brain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCHSTOP LAYERS AND CAPACITORS
- Publication number 20160233217
- Publication date Aug 11, 2016
- Intel Corporation
- RUTH A. BRAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCHSTOP LAYERS AND CAPACITORS
- Publication number 20150270331
- Publication date Sep 24, 2015
- Intel Corporation
- RUTH A. BRAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LANDING STRUCTURE FOR THROUGH-SILICON VIA
- Publication number 20150137368
- Publication date May 21, 2015
- Intel Corporation
- Christopher M. Pelto
- H01 - BASIC ELECTRIC ELEMENTS

Ruth A. Brain

Person

Patents Grantslast 30 patents

Metal space centered standard cell architecture to enable higher ce...

Replacement metal COB integration process for embedded DRAM

Via contact patterning method to increase edge placement error margin

Conductive cap-based approaches for conductive via fabrication and...

Ferroelectric-capacitor integration using novel multi-metal-level i...

Via contact patterning method to increase edge placement error margin

Plug and trench architectures for integrated circuits and methods o...

Conductive via and metal line end fabrication and structures result...

Power shared cell architecture

Etch-stop layer topography for advanced integrated circuit structur...

Decoupled via fill

Techniques for forming logic including integrated spin-transfer tor...

Etch-stop layer topography for advanced integrated circuit structur...

Via blocking layer

AVD hardmask for damascene patterning

Via blocking layer

Decoupled via fill

Decoupled via fill

Etchstop layers and capacitors

Method and structure to contact tight pitch conductive layers with...

Decoupled via fill

Via blocking layer

AVD hardmask for damascene patterning

Etchstop layers and capacitors

AVD hardmask for damascene patterning

Etchstop layers and capacitors

Etchstop layers and capacitors

Landing structure for through-silicon via

Fabrication of interconnects in a low-k interlayer dielectrics

Winged vias to increase overlay margin

Patents Applicationslast 30 patents

CELL ROWS WITH MIXED HEIGHTS AND MIXED NANORIBBON WIDTHS

PLUG & TRENCH ARCHITECTURES FOR INTEGRATED CIRCUITS & METHODS OF MA...

VIA CONTACT PATTERNING METHOD TO INCREASE EDGE PLACEMENT ERROR MARGIN

LINE PATTERNING IN INTEGRATED CIRCUIT DEVICES

METAL SPACE CENTERED STANDARD CELL ARCHITECTURE TO ENABLE HIGHER CE...

VIA CONTACT PATTERNING METHOD TO INCREASE EDGE PLACEMENT ERROR MARGIN

POWER SHARED CELL ARCHITECTURE

CONDUCTIVE VIA AND METAL LINE END FABRICATION AND STRUCTURES RESULT...

DECOUPLED VIA FILL

ETCH-STOP LAYER TOPOGRAPHY FOR ADVANCED INTEGRATED CIRCUIT STRUCTUR...

REPLACEMENT METAL COB INTEGRATION PROCESS FOR EMBEDDED DRAM

FERROELECTRIC-CAPACITOR INTEGRATION USING NOVEL MULTI-METAL-LEVEL I...

CONDUCTIVE CAP-BASED APPROACHES FOR CONDUCTIVE VIA FABRICATION AND...

DECOUPLED VIA FILL

PLUG & TRENCH ARCHITECTURES FOR INTEGRATED CIRCUITS & METHODS OF MA...

ETCH-STOP LAYER TOPOGRAPHY FOR ADVANCED INTEGRATED CIRCUIT STRUCTUR...

VIA BLOCKING LAYER

TECHNIQUES FOR FORMING LOGIC INCLUDING INTEGRATED SPIN-TRANSFER TOR...

APPROACHES FOR INTEGRATING STT-MRAM MEMORY ARRAYS INTO A LOGIC PROC...

DECOUPLED VIA FILL

VIA BLOCKING LAYER

AVD HARDMASK FOR DAMASCENE PATTERNING

DECOUPLED VIA FILL

METHOD AND STRUCTURE TO CONTACT TIGHT PITCH CONDUCTIVE LAYERS WITH...

VIA BLOCKING LAYER

ETCHSTOP LAYERS AND CAPACITORS

AVD HARDMASK FOR DAMASCENE PATTERNING

ETCHSTOP LAYERS AND CAPACITORS

ETCHSTOP LAYERS AND CAPACITORS

LANDING STRUCTURE FOR THROUGH-SILICON VIA