Ruth Patricia Jackson

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Cambridge, GB

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Patents Grantslast 30 patents

Information Patent Grant
Generate clock network using inverting integrated clock gate
- Patent number 11,163,929
- Issue date Nov 2, 2021
- Cadence Design Systems, Inc.
- William Robert Reece
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using negative-edge integrated clock gate in clock network
- Patent number 11,132,490
- Issue date Sep 28, 2021
- Cadence Design Systems, Inc.
- Ruth Patricia Jackson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for routing a clock net with multiple layer ranges
- Patent number 10,579,767
- Issue date Mar 3, 2020
- Cadence Design Systems, Inc.
- Zhuo Li
- G06 - COMPUTING CALCULATING COUNTING