Ryan C. Kinter

Person

Sammamish, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Fault detecting and fault tolerant multi-threaded processors
- Patent number 10,782,977
- Issue date Sep 22, 2020
- MIPS Tech, LLC
- Timothy Charles Mace
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coherent instruction cache utilizing cache-op execution resources
- Patent number 8,392,663
- Issue date Mar 5, 2013
- MIPS Technologies, Inc.
- Ryan C. Kinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for condensing trace information in a multi-pr...
- Patent number 8,230,202
- Issue date Jul 24, 2012
- MIPS Technologies, Inc.
- Thomas Benjamin Berg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multithreading microprocessor with optimized thread scheduler for i...
- Patent number 8,151,268
- Issue date Apr 3, 2012
- MIPS Technologies, Inc.
- Darren M. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Support for multiple coherence domains
- Patent number 8,131,941
- Issue date Mar 6, 2012
- MIPS Technologies, Inc.
- Ryan C. Kinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-tiered translation lookaside buffer hierarchy in a multithrea...
- Patent number 7,925,859
- Issue date Apr 12, 2011
- MIPS Technologies, Inc.
- Soumya Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor instruction using address index values to enable acc...
- Patent number 7,873,810
- Issue date Jan 18, 2011
- MIPS Technologies, Inc.
- Darren M. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction/skid buffers in a multithreading microprocessor that st...
- Patent number 7,853,777
- Issue date Dec 14, 2010
- MIPS Technologies, Inc.
- Darren M. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Avoiding livelock using intervention messages in multiple core proc...
- Patent number 7,769,958
- Issue date Aug 3, 2010
- MIPS Technologies, Inc.
- Ryan C. Kinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leaky-bucket thread scheduler in a multithreading microprocessor
- Patent number 7,752,627
- Issue date Jul 6, 2010
- MIPS Technologies, Inc.
- Darren M. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Avoiding livelock using a cache manager in multiple core processors
- Patent number 7,739,455
- Issue date Jun 15, 2010
- MIPS Technologies, Inc.
- Sanjay Vishin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping system and method for instruction set processing
- Patent number 7,711,926
- Issue date May 4, 2010
- MIPS Technologies, Inc.
- Ryan C. Kinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-ISA instruction fetch unit for a processor, and applications...
- Patent number 7,707,389
- Issue date Apr 27, 2010
- MIPS Technologies, Inc.
- Soumya Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multithreading instruction scheduler employing thread group priorities
- Patent number 7,681,014
- Issue date Mar 16, 2010
- MIPS Technologies, Inc.
- Michael Gottlieb Jensen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritizing thread selection partly based on stall likelihood prov...
- Patent number 7,664,936
- Issue date Feb 16, 2010
- MIPS Technologies, Inc.
- Michael Gottlieb Jensen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multithreading instruction scheduler employing thread group priorities
- Patent number 7,660,969
- Issue date Feb 9, 2010
- MIPS Technologies, Inc.
- Michael Gottlieb Jensen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multithreading microprocessor with optimized thread scheduler for i...
- Patent number 7,657,891
- Issue date Feb 2, 2010
- MIPS Technologies, Inc.
- Michael Gottlieb Jensen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for reducing data cache access power in a processor using w...
- Patent number 7,657,708
- Issue date Feb 2, 2010
- MIPS Technologies, Inc.
- Matthias Knoth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Micro tag array having way selection bits for reducing data cache a...
- Patent number 7,650,465
- Issue date Jan 19, 2010
- MIPS Technologies, Inc.
- Matthias Knoth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for redirection of operations between interfaces
- Patent number 7,634,619
- Issue date Dec 15, 2009
- MIPS Technologies, Inc.
- Gideon D. Intrater
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for discrete test access control of multiple c...
- Patent number 7,627,794
- Issue date Dec 1, 2009
- MIPS Technologies, Inc.
- Ryan C. Kinter
- G01 - MEASURING TESTING
Information Patent Grant
Interfacing external thread prioritizing policy enforcing logic wit...
- Patent number 7,613,904
- Issue date Nov 3, 2009
- MIPS Technologies, Inc.
- Darren M. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Smart memory based synchronization controller for a multi-threaded...
- Patent number 7,594,089
- Issue date Sep 22, 2009
- MIPS Technologies, Inc.
- Sanjay Vishin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-tiered translation lookaside buffer hierarchy in a multithrea...
- Patent number 7,558,939
- Issue date Jul 7, 2009
- MIPS Technologies, Inc.
- Soumya Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for discovering a scratch pad memory configura...
- Patent number 7,509,456
- Issue date Mar 24, 2009
- MIPS Technologies, Inc.
- Ryan C. Kinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor instructions for efficient bit stream extractions
- Patent number 7,315,937
- Issue date Jan 1, 2008
- MIPS Technologies, Inc.
- Darren M. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for redirection of operations between interfaces
- Patent number 6,961,819
- Issue date Nov 1, 2005
- MIPS Technologies, Inc.
- Gideon D. Intrater
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for discovering a scratch pad memory configura...
- Patent number 6,836,833
- Issue date Dec 28, 2004
- MIPS Technologies, Inc.
- Ryan C. Kinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scratchpad RAM memory accessible in parallel to a primary cache
- Patent number 6,430,655
- Issue date Aug 6, 2002
- MIPS Technologies, Inc.
- David A. Courtright
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FAULT DETECTING AND FAULT TOLERANT MULTI-THREADED PROCESSORS
- Publication number 20190073225
- Publication date Mar 7, 2019
- MIPS Tech, LLC
- Timothy Charles Mace
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method for Low Overhead Correlation of Multi-Processo...
- Publication number 20130067284
- Publication date Mar 14, 2013
- MIPS Technologies, Inc.
- Thomas Benjamin Berg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Support for Multiple Coherence Domains
- Publication number 20130031314
- Publication date Jan 31, 2013
- MIPS Technologies, Inc.
- Ryan C. Kinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multithreaded Operation of A Microprocessor Cache
- Publication number 20120290780
- Publication date Nov 15, 2012
- MIPS Technologies Inc.
- Ryan C. Kinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTITHREADING MICROPROCESSOR WITH OPTIMIZED THREAD SCHEDULER FOR I...
- Publication number 20100115244
- Publication date May 6, 2010
- MIPS Technologies, Inc.
- Michael Gottlieb Jensen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Three-Tiered Translation Lookaside Buffer Hierarchy in a Multithrea...
- Publication number 20090327649
- Publication date Dec 31, 2009
- MIPS Technologies, Inc.
- Soumya BANERJEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR LOW OVERHEAD CORRELATION OF MULTI-PROCESSO...
- Publication number 20090249046
- Publication date Oct 1, 2009
- MIPS Technologies, Inc.
- Thomas Benjamin BERG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR CONDENSING TRACE INFORMATION IN A MULTI-PR...
- Publication number 20090249045
- Publication date Oct 1, 2009
- MIPS Technologies, Inc.
- Thomas Benjamin BERG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COHERENT INSTRUCTION CACHE UTILIZING CACHE-OP EXECUTION RESOURCES
- Publication number 20090157981
- Publication date Jun 18, 2009
- MIPS Technologies, Inc.
- Ryan C. Kinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORT FOR MULTIPLE COHERENCE DOMAINS
- Publication number 20090083493
- Publication date Mar 26, 2009
- MIPS Technologies, Inc.
- Ryan C. Kinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Avoiding Livelock Using A Cache Manager in Multiple Core Processors
- Publication number 20080320230
- Publication date Dec 25, 2008
- MIPS Technologies Inc.
- Sanjay Vishin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reduced Handling of Writeback Data
- Publication number 20080320233
- Publication date Dec 25, 2008
- MIPS Technologies Inc.
- Ryan C. Kinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Avoiding Livelock Using Intervention Messages in Multiple Core Proc...
- Publication number 20080320231
- Publication date Dec 25, 2008
- MIPS Technologies Inc.
- Ryan C. Kinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor having a micro tag array that reduces data cache access p...
- Publication number 20080046652
- Publication date Feb 21, 2008
- MIPS Technologies, Inc.
- Matthias Knoth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods for reducing data cache access power in a processor, and ap...
- Publication number 20080046653
- Publication date Feb 21, 2008
- MIPS Technologies, Inc.
- Matthias Knoth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for discrete test access control of multiple c...
- Publication number 20070288814
- Publication date Dec 13, 2007
- MIPS Technologies, Inc.
- Ryan C. Kinter
- G01 - MEASURING TESTING
Information Patent Application
MULTITHREADING INSTRUCTION SCHEDULER EMPLOYING THREAD GROUP PRIORITIES
- Publication number 20070113053
- Publication date May 17, 2007
- MIPS Technologies, Inc.
- Michael Gottlieb Jensen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Three-tiered translation lookaside buffer hierarchy in a multithrea...
- Publication number 20060206686
- Publication date Sep 14, 2006
- MIPS Technologies, Inc.
- Soumya Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction/skid buffers in a multithreading microprocessor
- Publication number 20060179274
- Publication date Aug 10, 2006
- MIPS Technologies, Inc.
- Darren M. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Leaky-bucket thread scheduler in a multithreading microprocessor
- Publication number 20060179439
- Publication date Aug 10, 2006
- MIPS Technologies, Inc.
- Darren M. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multithreading processor including thread scheduler based on instru...
- Publication number 20060179280
- Publication date Aug 10, 2006
- MIPS Technologies, Inc.
- Michael Gottlieb Jensen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multithreading microprocessor with optimized thread scheduler for i...
- Publication number 20060179284
- Publication date Aug 10, 2006
- MIPS Technologies, Inc.
- Michael Gottlieb Jensen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bifurcated thread scheduler in a multithreading microprocessor
- Publication number 20060179279
- Publication date Aug 10, 2006
- MIPS Technologies, Inc.
- Darren M. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multithreading instruction scheduler employing thread group priorities
- Publication number 20060179281
- Publication date Aug 10, 2006
- MIPS Technologies, Inc.
- Michael Gottlieb Jensen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microprocessor instructions for efficient bit stream extractions
- Publication number 20060101258
- Publication date May 11, 2006
- MIPS Technologies Inc.
- Darren M. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microprocessor instruction using address index values to enable acc...
- Publication number 20060075208
- Publication date Apr 6, 2006
- MIPS Technologies Inc.
- Darren M. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for redirection of operations between interfaces
- Publication number 20060036808
- Publication date Feb 16, 2006
- MIPS Technologies, Inc.
- Gideon D. Intrater
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Smart memory based synchronization controller for a multi-threaded...
- Publication number 20050251639
- Publication date Nov 10, 2005
- MIPS Technologies, Inc. A Delaware Corporation
- Sanjay Vishin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for preventing duplicate matching entries in a...
- Publication number 20050182903
- Publication date Aug 18, 2005
- MIPS Technologies, Inc.
- Ryan C. Kinter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for recoding instructions
- Publication number 20050177707
- Publication date Aug 11, 2005
- MIPS Technologies, Inc.
- Soumya Banerjee
- G06 - COMPUTING CALCULATING COUNTING

Ryan C. Kinter

Person

Patents Grantslast 30 patents

Fault detecting and fault tolerant multi-threaded processors

Coherent instruction cache utilizing cache-op execution resources

Apparatus and method for condensing trace information in a multi-pr...

Multithreading microprocessor with optimized thread scheduler for i...

Support for multiple coherence domains

Three-tiered translation lookaside buffer hierarchy in a multithrea...

Microprocessor instruction using address index values to enable acc...

Instruction/skid buffers in a multithreading microprocessor that st...

Avoiding livelock using intervention messages in multiple core proc...

Leaky-bucket thread scheduler in a multithreading microprocessor

Avoiding livelock using a cache manager in multiple core processors

Mapping system and method for instruction set processing

Multi-ISA instruction fetch unit for a processor, and applications...

Multithreading instruction scheduler employing thread group priorities

Prioritizing thread selection partly based on stall likelihood prov...

Multithreading instruction scheduler employing thread group priorities

Multithreading microprocessor with optimized thread scheduler for i...

Methods for reducing data cache access power in a processor using w...

Micro tag array having way selection bits for reducing data cache a...

Method and apparatus for redirection of operations between interfaces

Apparatus and method for discrete test access control of multiple c...

Interfacing external thread prioritizing policy enforcing logic wit...

Smart memory based synchronization controller for a multi-threaded...

Three-tiered translation lookaside buffer hierarchy in a multithrea...

Apparatus and method for discovering a scratch pad memory configura...

Microprocessor instructions for efficient bit stream extractions

Method and apparatus for redirection of operations between interfaces

Apparatus and method for discovering a scratch pad memory configura...

Scratchpad RAM memory accessible in parallel to a primary cache

Patents Applicationslast 30 patents

FAULT DETECTING AND FAULT TOLERANT MULTI-THREADED PROCESSORS

Apparatus and Method for Low Overhead Correlation of Multi-Processo...

Support for Multiple Coherence Domains

Multithreaded Operation of A Microprocessor Cache

MULTITHREADING MICROPROCESSOR WITH OPTIMIZED THREAD SCHEDULER FOR I...

Three-Tiered Translation Lookaside Buffer Hierarchy in a Multithrea...

APPARATUS AND METHOD FOR LOW OVERHEAD CORRELATION OF MULTI-PROCESSO...

APPARATUS AND METHOD FOR CONDENSING TRACE INFORMATION IN A MULTI-PR...

COHERENT INSTRUCTION CACHE UTILIZING CACHE-OP EXECUTION RESOURCES

SUPPORT FOR MULTIPLE COHERENCE DOMAINS

Avoiding Livelock Using A Cache Manager in Multiple Core Processors

Reduced Handling of Writeback Data

Avoiding Livelock Using Intervention Messages in Multiple Core Proc...

Processor having a micro tag array that reduces data cache access p...

Methods for reducing data cache access power in a processor, and ap...

Apparatus and method for discrete test access control of multiple c...

MULTITHREADING INSTRUCTION SCHEDULER EMPLOYING THREAD GROUP PRIORITIES

Three-tiered translation lookaside buffer hierarchy in a multithrea...

Instruction/skid buffers in a multithreading microprocessor

Leaky-bucket thread scheduler in a multithreading microprocessor

Multithreading processor including thread scheduler based on instru...

Multithreading microprocessor with optimized thread scheduler for i...

Bifurcated thread scheduler in a multithreading microprocessor

Multithreading instruction scheduler employing thread group priorities

Microprocessor instructions for efficient bit stream extractions

Microprocessor instruction using address index values to enable acc...

Method and apparatus for redirection of operations between interfaces

Smart memory based synchronization controller for a multi-threaded...

Apparatus and method for preventing duplicate matching entries in a...

Method and apparatus for recoding instructions