Ryan C. Kivimagi

Person

Rochester, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for testing integrated circuits
- Patent number 7,681,095
- Issue date Mar 16, 2010
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for reducing wiring and required number of redundant elements
- Patent number 7,443,744
- Issue date Oct 28, 2008
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for testing integrated circuits
- Patent number 7,418,637
- Issue date Aug 26, 2008
- International Business Machines Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Flood mode implementation for continuous bitline local evaluation c...
- Patent number 7,283,411
- Issue date Oct 16, 2007
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Glitch protect valid cell and method for maintaining a desired stat...
- Patent number 7,224,594
- Issue date May 29, 2007
- International Business Machines
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Maskable dynamic logic
- Patent number 7,215,154
- Issue date May 8, 2007
- International Business Machines Corporation
- Derick Gardner Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flood mode implementation for continuous bitline local evaluation c...
- Patent number 7,133,320
- Issue date Nov 7, 2006
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and sum addressed cell encoder for enhanced compare and sear...
- Patent number 7,035,127
- Issue date Apr 25, 2006
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Method and Apparatus for Selectable Guaranteed Write Through
- Publication number 20090122626
- Publication date May 14, 2009
- Peter T. Freiburger
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCED SRAM REDUNDANCY CIRCUIT FOR REDUCING WIRING AND REQUIRED N...
- Publication number 20080273406
- Publication date Nov 6, 2008
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR TESTING INTEGRATED CIRCUITS
- Publication number 20080266985
- Publication date Oct 30, 2008
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and...
- Publication number 20080112219
- Publication date May 15, 2008
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and...
- Publication number 20080112237
- Publication date May 15, 2008
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Flood Mode Implementation for Continuous Bitline Local Evaluation C...
- Publication number 20070053231
- Publication date Mar 8, 2007
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for implementing power saving for content addr...
- Publication number 20070047282
- Publication date Mar 1, 2007
- International Business Machines Corporation
- Derick Gardner Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Glitch protect valid cell and method for maintaining a desired stat...
- Publication number 20070019454
- Publication date Jan 25, 2007
- International Business Machines (IBM) Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Maskable dynamic logic
- Publication number 20070018690
- Publication date Jan 25, 2007
- International Business Machines Corporation
- Derick Gardner Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Flood mode implementation for continuous bitline local evaluation c...
- Publication number 20060092727
- Publication date May 4, 2006
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND SUM ADDRESSED CELL ENCODER FOR ENHANCED COMPARE AND SEAR...
- Publication number 20060087873
- Publication date Apr 27, 2006
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Methods and apparatus for writing an LRU bit
- Publication number 20050125615
- Publication date Jun 9, 2005
- International Business Machines Corporation
- Peter T. Freiburger
- G11 - INFORMATION STORAGE
Information Patent Application
Methods and apparatus for testing integrated circuits
- Publication number 20050034037
- Publication date Feb 10, 2005
- International Business Machines Corporation,
- Derick G. Behrends
- G11 - INFORMATION STORAGE

Ryan C. Kivimagi

Person

Patents Grantslast 30 patents

Methods and apparatus for testing integrated circuits

Method for reducing wiring and required number of redundant elements

Methods and apparatus for testing integrated circuits

Flood mode implementation for continuous bitline local evaluation c...

Glitch protect valid cell and method for maintaining a desired stat...

Maskable dynamic logic

Flood mode implementation for continuous bitline local evaluation c...

Method and sum addressed cell encoder for enhanced compare and sear...

Patents Applicationslast 30 patents

Method and Apparatus for Selectable Guaranteed Write Through

ENHANCED SRAM REDUNDANCY CIRCUIT FOR REDUCING WIRING AND REQUIRED N...

METHODS AND APPARATUS FOR TESTING INTEGRATED CIRCUITS

Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and...

Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and...

Flood Mode Implementation for Continuous Bitline Local Evaluation C...

Method and apparatus for implementing power saving for content addr...

Glitch protect valid cell and method for maintaining a desired stat...

Maskable dynamic logic

Flood mode implementation for continuous bitline local evaluation c...

METHOD AND SUM ADDRESSED CELL ENCODER FOR ENHANCED COMPARE AND SEAR...

Methods and apparatus for writing an LRU bit

Methods and apparatus for testing integrated circuits