Ryan Fung

Person

Mississauga, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for performing fast incremental physical desig...
- Patent number 11,093,672
- Issue date Aug 17, 2021
- Altera Corporation
- Junaid Asim Khan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for memory interface calibration
- Patent number 10,832,787
- Issue date Nov 10, 2020
- Altera Corporation
- Ryan Fung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for performing fast incremental physical desig...
- Patent number 10,635,772
- Issue date Apr 28, 2020
- Altera Corporation
- Junaid Asim Khan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for memory interface calibration
- Patent number 10,332,612
- Issue date Jun 25, 2019
- Altera Corporation
- Ryan Fung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for source-synchronous information transfer and associate...
- Patent number 10,096,349
- Issue date Oct 9, 2018
- Altera Corporation
- Ryan Fung
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for performing efficient incremental compilation
- Patent number 10,073,941
- Issue date Sep 11, 2018
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit device configuration methods adapted to account...
- Patent number 10,037,396
- Issue date Jul 31, 2018
- Altera Corporation
- Ryan Fung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods for memory interface calibration
- Patent number 9,911,506
- Issue date Mar 6, 2018
- Ryan Fung
- G11 - INFORMATION STORAGE
Information Patent Grant
Metastability-hardened synchronization circuit
- Patent number 9,697,309
- Issue date Jul 4, 2017
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing timing analysis on calibrated p...
- Patent number 9,684,742
- Issue date Jun 20, 2017
- Altera Corporation
- Navid Azizi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for optimization of integrated circuits
- Patent number 9,600,622
- Issue date Mar 21, 2017
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and associated methods for parallelizing clustering and p...
- Patent number 9,594,859
- Issue date Mar 14, 2017
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing fast incremental physical desig...
- Patent number 9,569,574
- Issue date Feb 14, 2017
- Altera Corporation
- Junaid Asim Khan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for memory interface calibration
- Patent number 9,558,849
- Issue date Jan 31, 2017
- Altera Corporation
- Ryan Fung
- G11 - INFORMATION STORAGE
Information Patent Grant
Clocking for pipelined routing
- Patent number 9,360,884
- Issue date Jun 7, 2016
- Altera Corporation
- David Galloway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for protecting, optimizing, and reporting sync...
- Patent number 9,342,640
- Issue date May 17, 2016
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for considering paths influenced by different...
- Patent number 9,275,178
- Issue date Mar 1, 2016
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit device configuration methods adapted to account...
- Patent number 9,245,085
- Issue date Jan 26, 2016
- Altera Corporation
- Ryan Fung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for source-synchronous capture using a first-i...
- Patent number 9,201,449
- Issue date Dec 1, 2015
- Altera Corporation
- Ryan Fung
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatic asynchronous signal pipelining
- Patent number 9,183,336
- Issue date Nov 10, 2015
- Altera Corporation
- Mark Bourgeault
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for using metastability-hardened storage circuits in logi...
- Patent number 9,166,570
- Issue date Oct 20, 2015
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for composing and decomposing low-skew network...
- Patent number 9,124,271
- Issue date Sep 1, 2015
- Altera Corporation
- Ryan Fung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for reducing power spikes caused by clock netw...
- Patent number 9,024,683
- Issue date May 5, 2015
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for optimization of integrated circuits
- Patent number 8,949,763
- Issue date Feb 3, 2015
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for supporting low-latency external memory int...
- Patent number 8,930,597
- Issue date Jan 6, 2015
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gating and sampling a data strobe signal using a shared enable signal
- Patent number 8,929,162
- Issue date Jan 6, 2015
- Altera Corporation
- Joshua David Fender
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for performing timing analysis that accounts f...
- Patent number 8,930,175
- Issue date Jan 6, 2015
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing time domain jitter modeling
- Patent number 8,904,331
- Issue date Dec 2, 2014
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for integrating signal transition time modelin...
- Patent number 8,898,609
- Issue date Nov 25, 2014
- Altera Corporation
- Vadim Gouterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit device configuration methods adapted to account...
- Patent number 8,863,059
- Issue date Oct 14, 2014
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS FOR MEMORY INTERFACE CALIBRATION
- Publication number 20210082534
- Publication date Mar 18, 2021
- Altera Corporation
- Ryan Fung
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING FAST INCREMENTAL PHYSICAL DESIG...
- Publication number 20200257839
- Publication date Aug 13, 2020
- Altera Corporation
- Junaid Asim Khan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR MEMORY INTERFACE CALIBRATION
- Publication number 20190287638
- Publication date Sep 19, 2019
- Altera Corporation
- Ryan Fung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS FOR MEMORY INTERFACE CALIBRATION
- Publication number 20180151243
- Publication date May 31, 2018
- Altera Corporation
- Ryan Fung
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus For Source-Synchronous Information Transfer And Associate...
- Publication number 20160260465
- Publication date Sep 8, 2016
- Altera Corporation
- Ryan Fung
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCKING FOR PIPELINED ROUTING
- Publication number 20160239043
- Publication date Aug 18, 2016
- Altera Corporation
- David Galloway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT...
- Publication number 20160098507
- Publication date Apr 7, 2016
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Methods for Optimization of Integrated Circuits
- Publication number 20150135154
- Publication date May 14, 2015
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCKING FOR PIPELINED ROUTING
- Publication number 20150134870
- Publication date May 14, 2015
- Altera Corporation
- David Galloway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT...
- Publication number 20150033198
- Publication date Jan 29, 2015
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus for Using Metastability-Hardened Storage Circuits in Logi...
- Publication number 20130328607
- Publication date Dec 12, 2013
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS FOR SOURCE-SYNCHRONOUS INFORMATION TRANSFER AND ASSOCIATE...
- Publication number 20110299346
- Publication date Dec 8, 2011
- Ryan Fung
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS FOR USING METASTABILITY-HARDENED STORAGE CIRCUITS IN LOGI...
- Publication number 20110227625
- Publication date Sep 22, 2011
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
EFFICIENT DELAY ELEMENTS
- Publication number 20090015308
- Publication date Jan 15, 2009
- Altera Corporation
- Ryan FUNG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and methods for parallelizing integrated circuit computer...
- Publication number 20070192766
- Publication date Aug 16, 2007
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE DELAY CIRCUITRY
- Publication number 20060208785
- Publication date Sep 21, 2006
- Andy L. Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for mapping logic design memory into physical memory devices...
- Publication number 20050204325
- Publication date Sep 15, 2005
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Method and apparatus for performing fast incremental physical desig...

Methods for memory interface calibration

Method and apparatus for performing fast incremental physical desig...

Methods for memory interface calibration

Apparatus for source-synchronous information transfer and associate...

Method and apparatus for performing efficient incremental compilation

Integrated circuit device configuration methods adapted to account...

Methods for memory interface calibration

Metastability-hardened synchronization circuit

Method and apparatus for performing timing analysis on calibrated p...

Apparatus and methods for optimization of integrated circuits

Apparatus and associated methods for parallelizing clustering and p...

Method and apparatus for performing fast incremental physical desig...

Methods for memory interface calibration

Clocking for pipelined routing

Method and apparatus for protecting, optimizing, and reporting sync...

Method and apparatus for considering paths influenced by different...

Integrated circuit device configuration methods adapted to account...

Method and apparatus for source-synchronous capture using a first-i...

Automatic asynchronous signal pipelining

Apparatus for using metastability-hardened storage circuits in logi...

Method and apparatus for composing and decomposing low-skew network...

Method and apparatus for reducing power spikes caused by clock netw...

Apparatus and methods for optimization of integrated circuits

Method and apparatus for supporting low-latency external memory int...

Gating and sampling a data strobe signal using a shared enable signal

Method and apparatus for performing timing analysis that accounts f...

Method and apparatus for performing time domain jitter modeling

Method and apparatus for integrating signal transition time modelin...

Integrated circuit device configuration methods adapted to account...

Patents Applicationslast 30 patents

METHODS FOR MEMORY INTERFACE CALIBRATION

METHOD AND APPARATUS FOR PERFORMING FAST INCREMENTAL PHYSICAL DESIG...

METHODS FOR MEMORY INTERFACE CALIBRATION

METHODS FOR MEMORY INTERFACE CALIBRATION

Apparatus For Source-Synchronous Information Transfer And Associate...

CLOCKING FOR PIPELINED ROUTING

INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT...

Apparatus and Methods for Optimization of Integrated Circuits

CLOCKING FOR PIPELINED ROUTING

INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT...

Apparatus for Using Metastability-Hardened Storage Circuits in Logi...

APPARATUS FOR SOURCE-SYNCHRONOUS INFORMATION TRANSFER AND ASSOCIATE...

APPARATUS FOR USING METASTABILITY-HARDENED STORAGE CIRCUITS IN LOGI...

EFFICIENT DELAY ELEMENTS

Apparatus and methods for parallelizing integrated circuit computer...

VARIABLE DELAY CIRCUITRY

Method for mapping logic design memory into physical memory devices...