Ryan KEECH

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low resistance approaches for fabricating contacts and the resultin...
- Patent number 12,119,387
- Issue date Oct 15, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arsenic-doped epitaxial source/drain regions for NMOS
- Patent number 12,094,881
- Issue date Sep 17, 2024
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional integrated circuits (3DICs) including bottom gate...
- Patent number 11,996,404
- Issue date May 28, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source or drain structures for germanium N-channel devices
- Patent number 11,973,143
- Issue date Apr 30, 2024
- Intel Corporation
- Ryan Keech
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source or drain structures with vertical trenches
- Patent number 11,935,887
- Issue date Mar 19, 2024
- Intel Corporation
- Ryan Keech
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Top gate recessed channel CMOS thin film transistor in the back end...
- Patent number 11,929,320
- Issue date Mar 12, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High aspect ratio source or drain structures with abrupt dopant pro...
- Patent number 11,804,523
- Issue date Oct 31, 2023
- Intel Corporation
- Ryan Keech
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arsenic-doped epitaxial, source/drain regions for NMOS
- Patent number 11,610,889
- Issue date Mar 21, 2023
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source or drain structures with phosphorous and arsenic co-dopants
- Patent number 11,552,169
- Issue date Jan 10, 2023
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically stacked CMOS with upfront M0 interconnect
- Patent number 11,482,621
- Issue date Oct 25, 2022
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Top gate recessed channel CMOS thin film transistor in the back end...
- Patent number 11,328,988
- Issue date May 10, 2022
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional integrated circuits (3DICs) including bottom gate...
- Patent number 11,244,943
- Issue date Feb 8, 2022
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional integrated circuits (3DICs) including upper-level...
- Patent number 11,164,785
- Issue date Nov 2, 2021
- Intel Corporation
- Ashish Agrawal
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATI...
- Publication number 20240347610
- Publication date Oct 17, 2024
- Intel Corporation
- Koustav GANGULY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE OR DRAIN STRUCTURES FOR GERMANIUM N-CHANNEL DEVICES
- Publication number 20240258427
- Publication date Aug 1, 2024
- Intel Corporation
- Ryan KEECH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE OR DRAIN STRUCTURES WITH VERTICAL TRENCHES
- Publication number 20240170484
- Publication date May 23, 2024
- Intel Corporation
- Ryan KEECH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF...
- Publication number 20240136277
- Publication date Apr 25, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH ASPECT RATIO SOURCE OR DRAIN STRUCTURES WITH ABRUPT DOPANT PRO...
- Publication number 20240014268
- Publication date Jan 11, 2024
- Intel Corporation
- Ryan KEECH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARSENIC-DOPED EPITAXIAL SOURCE/DRAIN REGIONS FOR NMOS
- Publication number 20230197729
- Publication date Jun 22, 2023
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTORS WITH REDUCED EPITAXIAL SOURCE/DRAIN SPAN VIA ETCH-BACK...
- Publication number 20230095191
- Publication date Mar 30, 2023
- Intel Corporation
- Koustav Ganguly
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR IN THE BACK END...
- Publication number 20220223519
- Publication date Jul 14, 2022
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED INTERCONNECT STRUCTURES AND METHODS OF FABRICATION
- Publication number 20220199468
- Publication date Jun 23, 2022
- Intel Corporation
- Kimin Jun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE & DRAIN DOPANT DIFFUSION BARRIERS FOR N-TYPE GERMANIUM TRANS...
- Publication number 20220199402
- Publication date Jun 23, 2022
- Intel Corporation
- Koustav Ganguly
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW RESISTANCE APPROACHES FOR FABRICATING CONTACTS AND THE RESULTIN...
- Publication number 20220102521
- Publication date Mar 31, 2022
- Intel Corporation
- Gilbert DEWEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING BOTTOM GATE...
- Publication number 20220093586
- Publication date Mar 24, 2022
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED SOURC...
- Publication number 20210408283
- Publication date Dec 30, 2021
- Intel Corporation
- Ashish AGRAWAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED SOURC...
- Publication number 20210408284
- Publication date Dec 30, 2021
- Intel Corporation
- Ashish AGRAWAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATI...
- Publication number 20210408246
- Publication date Dec 30, 2021
- Intel Corporation
- Koustav GANGULY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED DUAL...
- Publication number 20210407996
- Publication date Dec 30, 2021
- Ashish AGRAWAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING BOTTOM GATE...
- Publication number 20210202476
- Publication date Jul 1, 2021
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING UPPER-LEVEL...
- Publication number 20210202319
- Publication date Jul 1, 2021
- Intel Corporation
- Ashish Agrawal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR IN THE BACK END...
- Publication number 20210202378
- Publication date Jul 1, 2021
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH ASPECT RATION SOURCE OR DRAIN STRUCTURES WITH ABRUPT DOPANT PR...
- Publication number 20210091181
- Publication date Mar 25, 2021
- Intel Corporation
- Ryan KEECH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE OR DRAIN STRUCTURES FOR GERMANIUM N-CHANNEL DEVICES
- Publication number 20200313001
- Publication date Oct 1, 2020
- Intel Corporation
- Ryan KEECH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE OR DRAIN STRUCTURES WITH VERTICAL TRENCHES
- Publication number 20200312842
- Publication date Oct 1, 2020
- Intel Corporation
- Ryan KEECH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE OR DRAIN STRUCTURES WITH PHOSPHOROUS AND ARSENIC CO-DOPANTS
- Publication number 20200312958
- Publication date Oct 1, 2020
- Intel Corporation
- Anand MURTHY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARSENIC-DOPED EPITAXIAL SOURCE/DRAIN REGIONS FOR NMOS
- Publication number 20200105754
- Publication date Apr 2, 2020
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICALLY STACKED CMOS WITH UPFRONT M0 INTERCONNECT
- Publication number 20200098921
- Publication date Mar 26, 2020
- Willy RACHMADY
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Low resistance approaches for fabricating contacts and the resultin...

Arsenic-doped epitaxial source/drain regions for NMOS

Three-dimensional integrated circuits (3DICs) including bottom gate...

Source or drain structures for germanium N-channel devices

Source or drain structures with vertical trenches

Top gate recessed channel CMOS thin film transistor in the back end...

High aspect ratio source or drain structures with abrupt dopant pro...

Arsenic-doped epitaxial, source/drain regions for NMOS

Source or drain structures with phosphorous and arsenic co-dopants

Vertically stacked CMOS with upfront M0 interconnect

Top gate recessed channel CMOS thin film transistor in the back end...

Three-dimensional integrated circuits (3DICs) including bottom gate...

Three-dimensional integrated circuits (3DICs) including upper-level...

Patents Applicationslast 30 patents

CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATI...

SOURCE OR DRAIN STRUCTURES FOR GERMANIUM N-CHANNEL DEVICES

SOURCE OR DRAIN STRUCTURES WITH VERTICAL TRENCHES

TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF...

HIGH ASPECT RATIO SOURCE OR DRAIN STRUCTURES WITH ABRUPT DOPANT PRO...

ARSENIC-DOPED EPITAXIAL SOURCE/DRAIN REGIONS FOR NMOS

TRANSISTORS WITH REDUCED EPITAXIAL SOURCE/DRAIN SPAN VIA ETCH-BACK...

TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR IN THE BACK END...

SELF-ALIGNED INTERCONNECT STRUCTURES AND METHODS OF FABRICATION

SOURCE & DRAIN DOPANT DIFFUSION BARRIERS FOR N-TYPE GERMANIUM TRANS...

LOW RESISTANCE APPROACHES FOR FABRICATING CONTACTS AND THE RESULTIN...

THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING BOTTOM GATE...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED SOURC...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED SOURC...

CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATI...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED DUAL...

THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING BOTTOM GATE...

THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING UPPER-LEVEL...

TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR IN THE BACK END...

HIGH ASPECT RATION SOURCE OR DRAIN STRUCTURES WITH ABRUPT DOPANT PR...

SOURCE OR DRAIN STRUCTURES FOR GERMANIUM N-CHANNEL DEVICES

SOURCE OR DRAIN STRUCTURES WITH VERTICAL TRENCHES

SOURCE OR DRAIN STRUCTURES WITH PHOSPHOROUS AND ARSENIC CO-DOPANTS

ARSENIC-DOPED EPITAXIAL SOURCE/DRAIN REGIONS FOR NMOS

VERTICALLY STACKED CMOS WITH UPFRONT M0 INTERCONNECT