Ryan T. Hirose

Person

Colorado Springs, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method to reduce program disturbs in non-volatile memory cells
- Patent number 10,262,747
- Issue date Apr 16, 2019
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to reduce program disturbs in non-volatile memory cells
- Patent number 10,204,691
- Issue date Feb 12, 2019
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture having two independently controlled voltage pumps
- Patent number 10,032,517
- Issue date Jul 24, 2018
- Cypress Semiconductor Corporation
- Ryan Tasuo Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture having two independently controlled voltage pumps
- Patent number 9,899,089
- Issue date Feb 20, 2018
- Cypress Semiconductor Corporation
- Ryan Tasuo Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to reduce program disturbs in non-volatile memory cells
- Patent number 9,847,137
- Issue date Dec 19, 2017
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to reduce program disturbs in non-volatile memory cells
- Patent number 9,431,124
- Issue date Aug 30, 2016
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for providing high voltage to memory devices
- Patent number 9,129,686
- Issue date Sep 8, 2015
- Cypress Semiconductor Corporation
- Ryan T Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Internal data compare for memory verification
- Patent number 9,007,843
- Issue date Apr 14, 2015
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to reduce program disturbs in non-volatile memory cells
- Patent number 8,988,938
- Issue date Mar 24, 2015
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory devices and systems
- Patent number 8,908,438
- Issue date Dec 9, 2014
- Cypress Semiconductor Corporation
- Ryan Tasuo Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for providing high voltage to memory devices
- Patent number 8,750,051
- Issue date Jun 10, 2014
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to reduce program disturbs in non-volatile memory cells
- Patent number 8,675,405
- Issue date Mar 18, 2014
- Cypress Semiconductor Corp.
- Bogdan Georgescu
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage tolerant row driver
- Patent number 8,599,618
- Issue date Dec 3, 2013
- Cypress Semiconductor Corp.
- Bogdan I. Georgescu
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory devices and systems
- Patent number 8,570,809
- Issue date Oct 29, 2013
- Cypress Semiconductor Corp.
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture having two independently controlled voltage pumps
- Patent number 8,542,541
- Issue date Sep 24, 2013
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture having two independently controlled voltage pumps
- Patent number 8,125,835
- Issue date Feb 28, 2012
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture having a reference current generator that provi...
- Patent number 7,969,804
- Issue date Jun 28, 2011
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Low impedance column multiplexer circuit and method
- Patent number 7,821,866
- Issue date Oct 26, 2010
- Cypress Semiconductor Corporation
- Vijay Kumar Srinivasa Raghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed, low supply voltage tolerant bootstrapped word line driv...
- Patent number 7,586,333
- Issue date Sep 8, 2009
- Cypress Semiconductor Corporation
- Vijay Kumar Srinivasa Raghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with leakage testing and read debug capability
- Patent number 7,545,694
- Issue date Jun 9, 2009
- Cypress Semiconductor Corporation
- Vijay Kumar Srinivasa Raghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiplexer circuit
- Patent number 7,471,135
- Issue date Dec 30, 2008
- Cypress Semiconductor Corp.
- Vijay Kumar Srinivasa Raghavan
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for discharging high voltage signals
- Patent number 7,012,456
- Issue date Mar 14, 2006
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit and method for reducing voltage stress in a memory decoder
- Patent number 6,654,309
- Issue date Nov 25, 2003
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor non-volatile memory device having a NAND cell structure
- Patent number 6,614,070
- Issue date Sep 2, 2003
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Level shifting circuit and method
- Patent number 6,590,420
- Issue date Jul 8, 2003
- Cypress Semiconductor Corporation
- Thomas M. Mnich
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor non-volatile latch device including non-volatile elem...
- Patent number 6,363,011
- Issue date Mar 26, 2002
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic regulation scheme for high speed charge pumps
- Patent number 6,272,029
- Issue date Aug 7, 2001
- United Microelectronics Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Asynchronously addressable clocked memory device and method of oper...
- Patent number 6,178,138
- Issue date Jan 23, 2001
- Celis Semiconductor Corporation
- Gary F. Derbenwick
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor non-volatile memory device having a NAND cell structure
- Patent number 6,163,048
- Issue date Dec 19, 2000
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor non-volatile device including embedded non-volatile e...
- Patent number 6,122,191
- Issue date Sep 19, 2000
- Cypress Semiconductor Corporation
- Ryan T. Hirose
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS
- Publication number 20180166140
- Publication date Jun 14, 2018
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan Tasuo Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
Method to Reduce Program Disturbs in Non-Volatile Memory Cells
- Publication number 20180068735
- Publication date Mar 8, 2018
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
Method to Reduce Program Disturbs in Non-Volatile Memory Cells
- Publication number 20170011807
- Publication date Jan 12, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS
- Publication number 20160005475
- Publication date Jan 7, 2016
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan Tasuo Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
Method to Reduce Program Disturbs in Non-Volatile Memory Cells
- Publication number 20150294731
- Publication date Oct 15, 2015
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR PROVIDING HIGH VOLTAGE TO MEMORY DEVICES
- Publication number 20140369136
- Publication date Dec 18, 2014
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
Method to Reduce Program Disturbs in Non-Volatile Memory Cells
- Publication number 20140301139
- Publication date Oct 9, 2014
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH VOLTAGE TOLERANT ROW DRIVER
- Publication number 20130170292
- Publication date Jul 4, 2013
- CYPRESS SEMICONDUCTOR CORPORATION
- Bogdan I. GEORGESCU
- G11 - INFORMATION STORAGE
Information Patent Application
INTERNAL DATA COMPARE FOR MEMORY VERIFICATION
- Publication number 20130141984
- Publication date Jun 6, 2013
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
FLASH MEMORY DEVICES AND SYSTEMS
- Publication number 20130141978
- Publication date Jun 6, 2013
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. HIROSE
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS
- Publication number 20120188826
- Publication date Jul 26, 2012
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Architecture Having Two Independently Controlled Voltage Pumps
- Publication number 20100074028
- Publication date Mar 25, 2010
- CYPRESS SEMICONDUCTOR CORPORATION
- Ryan T. Hirose
- G11 - INFORMATION STORAGE
Information Patent Application
High Speed, Leakage Tolerant, Double Bootstrapped Multiplexer Circu...
- Publication number 20080130375
- Publication date Jun 5, 2008
- Cypress Semiconductor Corp.
- Vijay Kumar Srinivasa Raghavan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
High Speed and Power Efficient Sense Amplifier With Leakage Testing...
- Publication number 20080042691
- Publication date Feb 21, 2008
- Vijay Kumar Srinivasa Raghavan
- G11 - INFORMATION STORAGE

Ryan T. Hirose

Person

Patents Grantslast 30 patents

Method to reduce program disturbs in non-volatile memory cells

Method to reduce program disturbs in non-volatile memory cells

Memory architecture having two independently controlled voltage pumps

Memory architecture having two independently controlled voltage pumps

Method to reduce program disturbs in non-volatile memory cells

Method to reduce program disturbs in non-volatile memory cells

Systems and methods for providing high voltage to memory devices

Internal data compare for memory verification

Method to reduce program disturbs in non-volatile memory cells

Flash memory devices and systems

Systems and methods for providing high voltage to memory devices

Method to reduce program disturbs in non-volatile memory cells

High voltage tolerant row driver

Flash memory devices and systems

Memory architecture having two independently controlled voltage pumps

Memory architecture having two independently controlled voltage pumps

Memory architecture having a reference current generator that provi...

Low impedance column multiplexer circuit and method

High speed, low supply voltage tolerant bootstrapped word line driv...

Sense amplifier with leakage testing and read debug capability

Multiplexer circuit

Circuit and method for discharging high voltage signals

Circuit and method for reducing voltage stress in a memory decoder

Semiconductor non-volatile memory device having a NAND cell structure

Level shifting circuit and method

Semiconductor non-volatile latch device including non-volatile elem...

Dynamic regulation scheme for high speed charge pumps

Asynchronously addressable clocked memory device and method of oper...

Semiconductor non-volatile memory device having a NAND cell structure

Semiconductor non-volatile device including embedded non-volatile e...

Patents Applicationslast 30 patents

MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS

Method to Reduce Program Disturbs in Non-Volatile Memory Cells

Method to Reduce Program Disturbs in Non-Volatile Memory Cells

MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS

Method to Reduce Program Disturbs in Non-Volatile Memory Cells

SYSTEMS AND METHODS FOR PROVIDING HIGH VOLTAGE TO MEMORY DEVICES

Method to Reduce Program Disturbs in Non-Volatile Memory Cells

HIGH VOLTAGE TOLERANT ROW DRIVER

INTERNAL DATA COMPARE FOR MEMORY VERIFICATION

FLASH MEMORY DEVICES AND SYSTEMS

MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS

Memory Architecture Having Two Independently Controlled Voltage Pumps

High Speed, Leakage Tolerant, Double Bootstrapped Multiplexer Circu...

High Speed and Power Efficient Sense Amplifier With Leakage Testing...