Ryan W. Sporer

Person

Mechanicville, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Photonics chips including a fully-depleted silicon-on-insulator fie...
- Patent number 12,176,351
- Issue date Dec 24, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for random code generation
- Patent number 11,907,685
- Issue date Feb 20, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Judson R. Holt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optical components undercut by a sealed cavity
- Patent number 11,650,382
- Issue date May 16, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Ryan Sporer
- G02 - OPTICS
Information Patent Grant
Well tap for an integrated circuit product and methods of forming s...
- Patent number 11,610,843
- Issue date Mar 21, 2023
- GLOBALFOUNDRIES U.S. INC.
- Hongru Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Photonics chips including a fully-depleted silicon-on-insulator fie...
- Patent number 11,569,268
- Issue date Jan 31, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure with different stress-inducing isolation dielectrics for...
- Patent number 11,450,573
- Issue date Sep 20, 2022
- GLOBALFOUNDRIES U.S. Inc.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enlarged waveguide for photonic integrated circuit without impactin...
- Patent number 11,409,037
- Issue date Aug 9, 2022
- GLOBALFOUNDRIES U.S. INC.
- Yusheng Bian
- G02 - OPTICS
Information Patent Grant
Differential SG/EG spacer integration with equivalent NFET/PFET spa...
- Patent number 11,217,678
- Issue date Jan 4, 2022
- GLOBALFOUNDRIES U.S. Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetrical lateral heterojunction bipolar transistors
- Patent number 11,127,843
- Issue date Sep 21, 2021
- GLOBALFOUNDRIES U.S. INC.
- Judson Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lateral heterojunction bipolar transistors with asymmetric junctions
- Patent number 11,094,805
- Issue date Aug 17, 2021
- GLOBALFOUNDRIES U.S. INC.
- Alexander Derrickson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch stop member in buried insulator of SOI substrate to reduce con...
- Patent number 10,943,814
- Issue date Mar 9, 2021
- GLOBALFOUNDRIES U.S. INC.
- Ryan W. Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Differential SG/EG spacer integration with equivalent NFET/PFET spa...
- Patent number 10,522,655
- Issue date Dec 31, 2019
- GLOBALFOUNDRIES Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post gate silicon germanium channel condensation and method for pro...
- Patent number 10,326,007
- Issue date Jun 18, 2019
- GLOBALFOUNDRIES Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique for patterning active regions of transistor elements in a...
- Patent number 10,217,660
- Issue date Feb 26, 2019
- GLOBALFOUNDRIES Inc.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Punchthrough stop layers for fin-type field-effect transistors
- Patent number 10,056,381
- Issue date Aug 21, 2018
- GLOBALFOUNDRIES Inc.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for late differential SOI thinning for improved FDSOI perfor...
- Patent number 10,050,119
- Issue date Aug 14, 2018
- GLOBALFOUNDRIES Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post gate silicon germanium channel condensation and method for pro...
- Patent number 10,043,893
- Issue date Aug 7, 2018
- GLOBALFOUNDRIES Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Spacer defined fin growth and differential fin width
- Patent number 9,875,936
- Issue date Jan 23, 2018
- GLOBALFOUNDRIES Inc.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Differential SG/EG spacer integration with equivalent NFET/PFET spa...
- Patent number 9,806,170
- Issue date Oct 31, 2017
- GLOBALFOUNDRIES Inc.
- George Robert Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming FinFET devices with substantially undoped channe...
- Patent number 9,634,143
- Issue date Apr 25, 2017
- GLOBALFOUNDRIES Inc.
- Jeremy A. Wahl
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
REFLECTORS FOR A PHOTONICS CHIP
- Publication number 20240402426
- Publication date Dec 5, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Yusheng Bian
- G02 - OPTICS
Information Patent Application
STRUCTURE INCLUDING HYBRID PLASMONIC WAVEGUIDE USING METAL SILICIDE...
- Publication number 20240111088
- Publication date Apr 4, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Yusheng Bian
- G02 - OPTICS
Information Patent Application
CLADDING STRUCTURE IN THE BACK END OF LINE OF PHOTONICS CHIPS
- Publication number 20230393340
- Publication date Dec 7, 2023
- GLOBALFOUNDRIES U.S. Inc.
- RYAN SPORER
- G02 - OPTICS
Information Patent Application
OPTICAL COMPONENTS UNDERCUT BY A SEALED CAVITY
- Publication number 20230128786
- Publication date Apr 27, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Ryan Sporer
- G02 - OPTICS
Information Patent Application
PHOTONICS CHIPS INCLUDING A FULLY-DEPLETED SILICON-ON-INSULATOR FIE...
- Publication number 20230047046
- Publication date Feb 16, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHOTONICS CHIPS INCLUDING A FULLY-DEPLETED SILICON-ON-INSULATOR FIE...
- Publication number 20230038887
- Publication date Feb 9, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WELL TAP FOR AN INTEGRATED CIRCUIT PRODUCT AND METHODS OF FORMING S...
- Publication number 20220285274
- Publication date Sep 8, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Hongru Ren
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENLARGED WAVEGUIDE FOR PHOTONIC INTEGRATED CIRCUIT WITHOUT IMPACTIN...
- Publication number 20220128762
- Publication date Apr 28, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Yusheng Bian
- G02 - OPTICS
Information Patent Application
STRUCTURE WITH DIFFERENT STRESS-INDUCING ISOLATION DIELECTRICS FOR...
- Publication number 20210398862
- Publication date Dec 23, 2021
- GLOBALFOUNDRIES U.S. Inc.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LATERAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH ASYMMETRIC JUNCTIONS
- Publication number 20210226044
- Publication date Jul 22, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Alexander Derrickson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR RANDOM CODE GENERATION
- Publication number 20210141610
- Publication date May 13, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Judson R. Holt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRICAL LATERAL HETEROJUNCTION BIPOLAR TRANSISTORS
- Publication number 20210091212
- Publication date Mar 25, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Judson Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH STOP MEMBER IN BURIED INSULATOR OF SOI SUBSTRATE TO REDUCE CON...
- Publication number 20210057271
- Publication date Feb 25, 2021
- GLOBALFOUNDRIES INC.
- Ryan W. Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPA...
- Publication number 20200083346
- Publication date Mar 12, 2020
- GLOBALFOUNDRIES INC.
- George Robert MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POST GATE SILICON GERMANIUM CHANNEL CONDENSATION AND METHOD FOR PRO...
- Publication number 20190043967
- Publication date Feb 7, 2019
- GLOBALFOUNDRIES INC.
- George Robert MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUE FOR PATTERNING ACTIVE REGIONS OF TRANSISTOR ELEMENTS IN A...
- Publication number 20190027400
- Publication date Jan 24, 2019
- GLOBALFOUNDRIES INC.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR LATE DIFFERENTIAL SOI THINNING FOR IMPROVED FDSOI PERFOR...
- Publication number 20180315832
- Publication date Nov 1, 2018
- GLOBALFOUNDRIES INC.
- George Robert MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPACER DEFINED FIN GROWTH AND DIFFERENTIAL FIN WIDTH
- Publication number 20180130712
- Publication date May 10, 2018
- GLOBALFOUNDRIES INC.
- Ryan SPORER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PUNCHTHROUGH STOP LAYERS FOR FIN-TYPE FIELD-EFFECT TRANSISTORS
- Publication number 20180069005
- Publication date Mar 8, 2018
- GLOBALFOUNDRIES INC.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR LATE DIFFERENTIAL SOI THINNING FOR IMPROVED FDSOI PERFOR...
- Publication number 20180069091
- Publication date Mar 8, 2018
- GLOBALFOUNDRIES Inc.
- George Robert MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPA...
- Publication number 20180012973
- Publication date Jan 11, 2018
- GLOBALFOUNDRIES INC.
- George Robert MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPA...
- Publication number 20170330953
- Publication date Nov 16, 2017
- GLOBALFOUNDRIES INC.
- George Robert MULFINGER
- H01 - BASIC ELECTRIC ELEMENTS

Ryan W. Sporer

Person

Patents Grantslast 30 patents

Photonics chips including a fully-depleted silicon-on-insulator fie...

Structure and method for random code generation

Optical components undercut by a sealed cavity

Well tap for an integrated circuit product and methods of forming s...

Photonics chips including a fully-depleted silicon-on-insulator fie...

Structure with different stress-inducing isolation dielectrics for...

Enlarged waveguide for photonic integrated circuit without impactin...

Differential SG/EG spacer integration with equivalent NFET/PFET spa...

Asymmetrical lateral heterojunction bipolar transistors

Lateral heterojunction bipolar transistors with asymmetric junctions

Etch stop member in buried insulator of SOI substrate to reduce con...

Differential SG/EG spacer integration with equivalent NFET/PFET spa...

Post gate silicon germanium channel condensation and method for pro...

Technique for patterning active regions of transistor elements in a...

Punchthrough stop layers for fin-type field-effect transistors

Method for late differential SOI thinning for improved FDSOI perfor...

Post gate silicon germanium channel condensation and method for pro...

Spacer defined fin growth and differential fin width

Differential SG/EG spacer integration with equivalent NFET/PFET spa...

Methods of forming FinFET devices with substantially undoped channe...

Patents Applicationslast 30 patents

REFLECTORS FOR A PHOTONICS CHIP

STRUCTURE INCLUDING HYBRID PLASMONIC WAVEGUIDE USING METAL SILICIDE...

CLADDING STRUCTURE IN THE BACK END OF LINE OF PHOTONICS CHIPS

OPTICAL COMPONENTS UNDERCUT BY A SEALED CAVITY

PHOTONICS CHIPS INCLUDING A FULLY-DEPLETED SILICON-ON-INSULATOR FIE...

PHOTONICS CHIPS INCLUDING A FULLY-DEPLETED SILICON-ON-INSULATOR FIE...

WELL TAP FOR AN INTEGRATED CIRCUIT PRODUCT AND METHODS OF FORMING S...

ENLARGED WAVEGUIDE FOR PHOTONIC INTEGRATED CIRCUIT WITHOUT IMPACTIN...

STRUCTURE WITH DIFFERENT STRESS-INDUCING ISOLATION DIELECTRICS FOR...

LATERAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH ASYMMETRIC JUNCTIONS

STRUCTURE AND METHOD FOR RANDOM CODE GENERATION

ASYMMETRICAL LATERAL HETEROJUNCTION BIPOLAR TRANSISTORS

ETCH STOP MEMBER IN BURIED INSULATOR OF SOI SUBSTRATE TO REDUCE CON...

DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPA...

POST GATE SILICON GERMANIUM CHANNEL CONDENSATION AND METHOD FOR PRO...

TECHNIQUE FOR PATTERNING ACTIVE REGIONS OF TRANSISTOR ELEMENTS IN A...

METHOD FOR LATE DIFFERENTIAL SOI THINNING FOR IMPROVED FDSOI PERFOR...

SPACER DEFINED FIN GROWTH AND DIFFERENTIAL FIN WIDTH

PUNCHTHROUGH STOP LAYERS FOR FIN-TYPE FIELD-EFFECT TRANSISTORS

METHOD FOR LATE DIFFERENTIAL SOI THINNING FOR IMPROVED FDSOI PERFOR...

DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPA...

DIFFERENTIAL SG/EG SPACER INTEGRATION WITH EQUIVALENT NFET/PFET SPA...