S. Babar Raza

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Logic for implementing a dual clock domain read access with predict...
- Patent number 7,934,057
- Issue date Apr 26, 2011
- Cypress Semiconductor Corporation
- S. Babar Raza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device that provides the functionality of dual-ported memory using...
- Patent number 7,738,496
- Issue date Jun 15, 2010
- Cypress Semiconductor Corporation
- S. Babar Raza
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for aggregating Ethernet streams
- Patent number 7,382,805
- Issue date Jun 3, 2008
- Cypress Semiconductor Corporation
- S. Babar Raza
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and device for selecting one of multiple clock signals based...
- Patent number 7,343,510
- Issue date Mar 11, 2008
- Cypress Semiconductor Corporation
- Mark Ross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and architecture for synchronizing a path generator and/or e...
- Patent number 7,334,147
- Issue date Feb 19, 2008
- Cypress Semiconductor Corporation
- S. Babar Raza
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for staging concurrent accesses to a memory addre...
- Patent number 7,184,359
- Issue date Feb 27, 2007
- Cypress Semiconductor Corp.
- Walter F. Bridgewater
- G11 - INFORMATION STORAGE
Information Patent Grant
Logic for generating multicast/unicast address (es)
- Patent number 7,016,349
- Issue date Mar 21, 2006
- Cypress Semiconductor Corp.
- S. Babar Raza
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Architecture for implementing virtual multiqueue fifos
- Patent number 6,925,506
- Issue date Aug 2, 2005
- Cypress Semiconductor Corp.
- S. Babar Raza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, architecture and circuitry for controlling pulse width in a...
- Patent number 6,917,661
- Issue date Jul 12, 2005
- Cypress Semiconductor Corp.
- Paul H. Scott
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configurable fast clock detection logic with programmable resolution
- Patent number 6,816,979
- Issue date Nov 9, 2004
- Cypress Semiconductor Corp.
- Jiann-Cheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic for providing arbitration for synchronous dual-port memory
- Patent number 6,816,955
- Issue date Nov 9, 2004
- Cypress Semiconductor Corp.
- S. Babar Raza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FIFO read interface protocol
- Patent number 6,810,098
- Issue date Oct 26, 2004
- Cypress Semiconductor Corp.
- Somnath Paul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Out-of-band look-ahead arbitration method and/or architecture
- Patent number 6,715,021
- Issue date Mar 30, 2004
- Cypress Semiconductor Corp.
- Somnath Paul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Overhead serial communication scheme
- Patent number 6,665,265
- Issue date Dec 16, 2003
- Cypress Semiconductor Corp.
- S. Babar Raza
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit, system, and method for programmably setting an input to a...
- Patent number 6,657,472
- Issue date Dec 2, 2003
- Cypress Semiconductor Corp.
- S. Babar Raza
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for width and depth expansion in a multi-queue...
- Patent number 6,640,300
- Issue date Oct 28, 2003
- Cypress Semiconductor Corp.
- S. Babar Raza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for multi-queue storage element
- Patent number 6,640,267
- Issue date Oct 28, 2003
- Cypress Semiconductor Corp.
- S. Babar Raza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic for initializing the depth of the queue pointer memory
- Patent number 6,631,455
- Issue date Oct 7, 2003
- Cypress Semiconductor Corp.
- S. Babar Raza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit, method and/or architecture for improving the performance o...
- Patent number 6,628,656
- Issue date Sep 30, 2003
- Cypress Semiconductor Corp.
- S. Babar Raza
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Fifo read interface protocol
- Patent number 6,629,226
- Issue date Sep 30, 2003
- Cypress Semiconductor Corp.
- Somnath Paul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and/or architecture for implementing queue expansion in mult...
- Patent number 6,625,711
- Issue date Sep 23, 2003
- Cypress Semiconductor Corp.
- S. Babar Raza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit, method and/or architecture for improving the performance o...
- Patent number 6,625,177
- Issue date Sep 23, 2003
- Cypress Semiconductor Corp.
- S. Babar Raza
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Highly scalable architecture for implementing switch fabrics with q...
- Patent number 6,603,771
- Issue date Aug 5, 2003
- Cypress Semiconductor Corp.
- S. Babar Raza
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit and method for supporting multicast/broadcast operations in...
- Patent number 6,584,517
- Issue date Jun 24, 2003
- Cypress Semiconductor Corp.
- S. Babar Raza
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and logic for initializing the forward-pointer memory during...
- Patent number 6,581,144
- Issue date Jun 17, 2003
- Cypress Semiconductor Corp.
- S. Babar Raza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and logic for storing and extracting in-band multicast port...
- Patent number 6,578,118
- Issue date Jun 10, 2003
- Cypress Semiconductor Corp.
- S. Babar Raza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design architecture for a parallel and serial programming interface
- Patent number 6,510,487
- Issue date Jan 21, 2003
- Cypress Semiconductor Corp.
- S. Babar Raza
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and architecture for synchronizing a transport and path over...
- Patent number 6,502,197
- Issue date Dec 31, 2002
- Cypress Semiconductor Corp.
- S. Babar Raza
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods for maximizing routability in a programmable interconnect m...
- Patent number 6,243,664
- Issue date Jun 5, 2001
- Cypress Semiconductor Corporation
- Hagop A. Nazarian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for a dual segment dual speed repeater
- Patent number 6,229,811
- Issue date May 8, 2001
- Cypress Semiconductor Corp.
- S. Babar Raza
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

S. Babar Raza

Person

Patents Grantslast 30 patents

Logic for implementing a dual clock domain read access with predict...

Device that provides the functionality of dual-ported memory using...

Method and apparatus for aggregating Ethernet streams

Method and device for selecting one of multiple clock signals based...

Method and architecture for synchronizing a path generator and/or e...

System and method for staging concurrent accesses to a memory addre...

Logic for generating multicast/unicast address (es)

Architecture for implementing virtual multiqueue fifos

Method, architecture and circuitry for controlling pulse width in a...

Configurable fast clock detection logic with programmable resolution

Logic for providing arbitration for synchronous dual-port memory

FIFO read interface protocol

Out-of-band look-ahead arbitration method and/or architecture

Overhead serial communication scheme

Circuit, system, and method for programmably setting an input to a...

Method and apparatus for width and depth expansion in a multi-queue...

Architecture for multi-queue storage element

Logic for initializing the depth of the queue pointer memory

Circuit, method and/or architecture for improving the performance o...

Fifo read interface protocol

Method and/or architecture for implementing queue expansion in mult...

Circuit, method and/or architecture for improving the performance o...

Highly scalable architecture for implementing switch fabrics with q...

Circuit and method for supporting multicast/broadcast operations in...

Method and logic for initializing the forward-pointer memory during...

Method and logic for storing and extracting in-band multicast port...

Design architecture for a parallel and serial programming interface

Method and architecture for synchronizing a transport and path over...

Methods for maximizing routability in a programmable interconnect m...

Architecture for a dual segment dual speed repeater