S. Craig Nelson

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
MicroTLB and micro tag for reducing power in a processor
- Patent number 7,117,290
- Issue date Oct 3, 2006
- Advanced Micro Devices, Inc.
- Gene W. Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing instruction TLB accesses
- Patent number 7,076,635
- Issue date Jul 11, 2006
- Advanced Micro Devices, Inc.
- Michael G. Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split latency decoding
- Patent number 6,844,831
- Issue date Jan 18, 2005
- Advanced Micro Devices, Inc.
- S. Craig Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for cache memory
- Patent number 5,568,632
- Issue date Oct 22, 1996
- LSI Logic Corporation
- S. Craig Nelson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MicroTLB and micro TAG for reducing power in a processor
- Publication number 20050050277
- Publication date Mar 3, 2005
- Advanced Micro Devices, Inc.
- Gene W. Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low power way-predicted cache
- Publication number 20050050278
- Publication date Mar 3, 2005
- Advanced Micro Devices, Inc.
- Stephan G. Meier
- G06 - COMPUTING CALCULATING COUNTING