S. Reji Kumar

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University Place, WA, US

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Patents Grantslast 30 patents

Information Patent Grant
Dual clock domain deskew circuit
- Patent number 7,656,983
- Issue date Feb 2, 2010
- Intel Corporation
- Daniel S. Klowden
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Training pattern based de-skew mechanism and frame alignment
- Patent number 7,500,131
- Issue date Mar 3, 2009
- Intel Corporation
- Adarsh Panikkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delaying lanes in order to align all lanes crossing between two clo...
- Patent number 7,346,795
- Issue date Mar 18, 2008
- Intel Corporation
- Daniel S. Klowden
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Selective tracking of serial communication link data
- Publication number 20080130815
- Publication date Jun 5, 2008
- S. Reji Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dual clock domain deskew circuit
- Publication number 20080080654
- Publication date Apr 3, 2008
- Daniel S. Klowden
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Keep-out asynchronous clock alignment scheme
- Publication number 20060146967
- Publication date Jul 6, 2006
- Adarsh Panikkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Keep-out clock alignment cycle coherency protection
- Publication number 20060149987
- Publication date Jul 6, 2006
- Daniel S. Klowden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Training pattern based de-skew mechanism and frame alignment
- Publication number 20060053328
- Publication date Mar 9, 2006
- Adarsh Panikkar
- G06 - COMPUTING CALCULATING COUNTING