Saad Monasa

Person

Sacramento, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Encoding additional states in a three-dimensional crosspoint memory...
- Patent number 12,249,372
- Issue date Mar 11, 2025
- Intel Corporation
- Rouhollah Mousavi Iraei
- G11 - INFORMATION STORAGE
Information Patent Grant
DDR flash implementation with direct register access to legacy flas...
- Patent number 8,006,029
- Issue date Aug 23, 2011
- Intel Corporation
- Ramkarthik Ganesan
- G11 - INFORMATION STORAGE
Information Patent Grant
DDR flash implementation with hybrid row buffers and direct access...
- Patent number 7,707,378
- Issue date Apr 27, 2010
- Intel Corporation
- Ramkarthik Ganesan
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level memory cell sensing
- Patent number 7,551,489
- Issue date Jun 23, 2009
- Intel Corporation
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-stage digital-to-analog converter
- Patent number 7,265,698
- Issue date Sep 4, 2007
- Intel Corporation
- Richard E. Fackenthal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-stage digital-to-analog converter
- Patent number 7,034,732
- Issue date Apr 25, 2006
- Intel Corporation
- Richard E. Fackenthal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Enabling an interim density for top boot flash memories
- Patent number 6,707,749
- Issue date Mar 16, 2004
- Intel Corporation
- Quan H. Ngo
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ENCODING ADDITIONAL STATES IN A THREE-DIMENSIONAL CROSSPOINT MEMORY...
- Publication number 20230064007
- Publication date Mar 2, 2023
- Intel Corporation
- Rouhollah Mousavi Iraei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DDR FLASH IMPLEMENTATION WITH DIRECT REGISTER ACCESS TO LEGACY FLAS...
- Publication number 20120191898
- Publication date Jul 26, 2012
- Ramkarthik Ganesan
- G11 - INFORMATION STORAGE
Information Patent Application
DDR flash implementation with row buffer interface to legacy flash...
- Publication number 20080133820
- Publication date Jun 5, 2008
- Ramkarthik Ganesan
- G11 - INFORMATION STORAGE
Information Patent Application
DDR flash implementation with hybrid row buffers and direct access...
- Publication number 20080133819
- Publication date Jun 5, 2008
- Ramkarthik Ganesan
- G11 - INFORMATION STORAGE
Information Patent Application
DDR flash implementation with direct register access to legacy flas...
- Publication number 20080133821
- Publication date Jun 5, 2008
- Ramkarthik Ganesan
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-level memory cell sensing
- Publication number 20070171708
- Publication date Jul 26, 2007
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-stage digital-to-analog converter
- Publication number 20060145905
- Publication date Jul 6, 2006
- Richard E. Fackenthal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Data latch pre-equalization
- Publication number 20050285631
- Publication date Dec 29, 2005
- Intel Corporation
- Matthew Goldman
- G11 - INFORMATION STORAGE
Information Patent Application
ENABLING AN INTERIM DENSITY FOR TOP BOOT FLASH MEMORIES
- Publication number 20040032789
- Publication date Feb 19, 2004
- Quan H. Ngo
- G11 - INFORMATION STORAGE

Saad Monasa

Person

Patents Grantslast 30 patents

Encoding additional states in a three-dimensional crosspoint memory...

DDR flash implementation with direct register access to legacy flas...

DDR flash implementation with hybrid row buffers and direct access...

Multi-level memory cell sensing

Multi-stage digital-to-analog converter

Multi-stage digital-to-analog converter

Enabling an interim density for top boot flash memories

Patents Applicationslast 30 patents

ENCODING ADDITIONAL STATES IN A THREE-DIMENSIONAL CROSSPOINT MEMORY...

DDR FLASH IMPLEMENTATION WITH DIRECT REGISTER ACCESS TO LEGACY FLAS...

DDR flash implementation with row buffer interface to legacy flash...

DDR flash implementation with hybrid row buffers and direct access...

DDR flash implementation with direct register access to legacy flas...

Multi-level memory cell sensing

Multi-stage digital-to-analog converter

Data latch pre-equalization

ENABLING AN INTERIM DENSITY FOR TOP BOOT FLASH MEMORIES