Sabyasachi Das

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low-power static signoff verification from within an implementation...
- Patent number 11,947,885
- Issue date Apr 2, 2024
- Synopsys, Inc.
- Meera Viswanath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to perform secondary-PG aware buffering in IC design flow
- Patent number 11,449,660
- Issue date Sep 20, 2022
- Synopsys, Inc.
- Jin Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated pipeline insertion on a bus
- Patent number 10,970,446
- Issue date Apr 6, 2021
- XLNX, INC.
- Jeffrey H. Seltzer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-placement and post-routing physical synthesis for multi-die in...
- Patent number 10,839,125
- Issue date Nov 17, 2020
- Xilinx, Inc.
- Sreesan Venkatakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing optimization of memory blocks in a programmable IC
- Patent number 10,699,053
- Issue date Jun 30, 2020
- Xilinx, Inc.
- Zhiyong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register pull-out for sequential circuit blocks in circuit designs
- Patent number 10,642,951
- Issue date May 5, 2020
- Xilinx, Inc.
- Govinda Keshavdas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical synthesis within placement
- Patent number 10,572,621
- Issue date Feb 25, 2020
- Xilinx, Inc.
- Zhiyong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Targeted delay optimization through programmable clock delays
- Patent number 10,565,334
- Issue date Feb 18, 2020
- Xilinx, Inc.
- Ruibing Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of delay circuits for avoiding hold violations
- Patent number 10,540,463
- Issue date Jan 21, 2020
- Xilinx, Inc.
- Maheshwar Chandrasekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing-closure methodology involving clock network in hardware designs
- Patent number 10,528,697
- Issue date Jan 7, 2020
- Xilinx, Inc.
- Wei Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical synthesis for multi-die integrated circuit technology
- Patent number 10,496,777
- Issue date Dec 3, 2019
- Xilinx, Inc.
- Sreesan Venkatakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logical and physical optimizations for partial reconfiguration desi...
- Patent number 10,303,648
- Issue date May 28, 2019
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design implementation using control-set based merging and m...
- Patent number 10,242,150
- Issue date Mar 26, 2019
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural network based physical synthesis for circuit designs
- Patent number 10,192,016
- Issue date Jan 29, 2019
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device design implementations with multiplexer t...
- Patent number 10,068,045
- Issue date Sep 4, 2018
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fanout optimization to facilitate timing improvement in circuit des...
- Patent number 9,965,581
- Issue date May 8, 2018
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable integrated circuit design flow using timing-driven pip...
- Patent number 9,836,568
- Issue date Dec 5, 2017
- Xilinx, Inc.
- Ilya K. Ganusov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-placement and pre-routing processing of critical paths in a ci...
- Patent number 9,773,083
- Issue date Sep 26, 2017
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look-up table restructuring for timing closure in circuit designs
- Patent number 9,767,247
- Issue date Sep 19, 2017
- Xilinx, Inc.
- Ruibing Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-routing structural netlist optimization for circuit designs
- Patent number 9,646,126
- Issue date May 9, 2017
- Xilinx, Inc.
- Ruibing Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interactive multi-step physical synthesis
- Patent number 9,613,173
- Issue date Apr 4, 2017
- Xilinx, Inc.
- Rajat Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Opportunistic candidate path selection during physical optimization...
- Patent number 9,483,597
- Issue date Nov 1, 2016
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective addition of clock buffers to a circuit design
- Patent number 9,235,660
- Issue date Jan 12, 2016
- Xilinx, Inc.
- Ruibing Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical optimization for timing closure for an integrated circuit
- Patent number 8,984,462
- Issue date Mar 17, 2015
- Xilinx, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
NEURAL NETWORK BASED PHYSICAL SYNTHESIS FOR CIRCUIT DESIGNS
- Publication number 20180203956
- Publication date Jul 19, 2018
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERACTIVE MULTI-STEP PHYSICAL SYNTHESIS
- Publication number 20170098024
- Publication date Apr 6, 2017
- Xilinx, Inc.
- Rajat Aggarwal
- G06 - COMPUTING CALCULATING COUNTING

Sabyasachi Das

Person

Patents Grantslast 30 patents

Low-power static signoff verification from within an implementation...

Method to perform secondary-PG aware buffering in IC design flow

Automated pipeline insertion on a bus

Post-placement and post-routing physical synthesis for multi-die in...

Timing optimization of memory blocks in a programmable IC

Register pull-out for sequential circuit blocks in circuit designs

Physical synthesis within placement

Targeted delay optimization through programmable clock delays

Placement of delay circuits for avoiding hold violations

Timing-closure methodology involving clock network in hardware designs

Physical synthesis for multi-die integrated circuit technology

Logical and physical optimizations for partial reconfiguration desi...

Circuit design implementation using control-set based merging and m...

Neural network based physical synthesis for circuit designs

Programmable logic device design implementations with multiplexer t...

Fanout optimization to facilitate timing improvement in circuit des...

Programmable integrated circuit design flow using timing-driven pip...

Post-placement and pre-routing processing of critical paths in a ci...

Look-up table restructuring for timing closure in circuit designs

Post-routing structural netlist optimization for circuit designs

Interactive multi-step physical synthesis

Opportunistic candidate path selection during physical optimization...

Selective addition of clock buffers to a circuit design

Physical optimization for timing closure for an integrated circuit

Patents Applicationslast 30 patents

NEURAL NETWORK BASED PHYSICAL SYNTHESIS FOR CIRCUIT DESIGNS

INTERACTIVE MULTI-STEP PHYSICAL SYNTHESIS