Sachin Joshi

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low power signaling for data transfer
- Patent number 9,245,625
- Issue date Jan 26, 2016
- Broadcom Corporation
- Sachin Joshi
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to boost word-line voltage using parasitic capacitances
- Patent number 9,245,602
- Issue date Jan 26, 2016
- Broadcom Corporation
- Sachin Joshi
- G11 - INFORMATION STORAGE
Information Patent Grant
Low swing dynamic circuit
- Patent number 8,890,572
- Issue date Nov 18, 2014
- Broadcom Corporation
- Sachin Joshi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Compiling regular expressions for programmable content addressable...
- Patent number 7,924,590
- Issue date Apr 12, 2011
- Netlogic Microsystems, Inc.
- Alexei Starovoitov
- G11 - INFORMATION STORAGE
Information Patent Grant
Comparator circuit
- Patent number 7,919,991
- Issue date Apr 5, 2011
- Netlogic Microsystems, Inc.
- Sachin Joshi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reformulating regular expressions into architecture-dependent bit g...
- Patent number 7,916,510
- Issue date Mar 29, 2011
- Netlogic Microsystems, Inc.
- Alexei Starovoitov
- G11 - INFORMATION STORAGE
Information Patent Grant
Power reduction in a content addressable memory having programmable...
- Patent number 7,881,125
- Issue date Feb 1, 2011
- Netlogic Microsystems, Inc.
- Maheshwaran Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory having selectively interconnected rows o...
- Patent number 7,876,590
- Issue date Jan 25, 2011
- Netlogic Microsystems, Inc.
- Sachin Joshi
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addresable memory having selectively interconnected counter...
- Patent number 7,826,242
- Issue date Nov 2, 2010
- Netlogic Microsystems, Inc.
- Sachin Joshi
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addresable memory having programmable interconnect structure
- Patent number 7,821,844
- Issue date Oct 26, 2010
- Netlogic Microsystems, Inc.
- Maheshwaran Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addresable memory having selectively interconnected counter...
- Patent number 7,660,140
- Issue date Feb 9, 2010
- NetLogic Microsystems, Inc.
- Sachin Joshi
- G11 - INFORMATION STORAGE
Information Patent Grant
Regular expression search engine
- Patent number 7,656,716
- Issue date Feb 2, 2010
- NetLogic Microsystems, Inc.
- Varadarajan Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory having programmable interconnect structure
- Patent number 7,643,353
- Issue date Jan 5, 2010
- NetLogic Microsystems, Inc.
- Maheshwaran Srinivasan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES TO BOOST WORD-LINE VOLTAGE USING PARASITIC CAPACITANCES
- Publication number 20160099029
- Publication date Apr 7, 2016
- BROADCOM CORPORATION
- Sachin JOSHI
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES TO BOOST WORD-LINE VOLTAGE USING PARASITIC CAPACITANCES
- Publication number 20150162058
- Publication date Jun 11, 2015
- BROADCOM CORPORATION
- Sachin JOSHI
- G11 - INFORMATION STORAGE
Information Patent Application
Low Power Signaling for Data Transfer
- Publication number 20140089550
- Publication date Mar 27, 2014
- BROADCOM CORPORATION
- Sachin JOSHI
- G11 - INFORMATION STORAGE
Information Patent Application
Low Swing Dynamic Circuit
- Publication number 20140077840
- Publication date Mar 20, 2014
- BROADCOM CORPORATION
- Sachin JOSHI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONTENT ADDRESSABLE MEMORY HAVING PROGRAMMABLE INTERCONNECT STRUCTURE
- Publication number 20100321970
- Publication date Dec 23, 2010
- Maheshwaran Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
CONTENT ADDRESSABLE MEMORY HAVING SELECTIVELY INTERCONNECTED COUNTE...
- Publication number 20100321971
- Publication date Dec 23, 2010
- Sachin Joshi
- G11 - INFORMATION STORAGE
Information Patent Application
CONTENT ADDRESABLE MEMORY HAVING PROGRAMMABLE INTERCONNECT STRUCTURE
- Publication number 20100054012
- Publication date Mar 4, 2010
- Maheshwaran Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
CONTENT ADDRESABLE MEMORY HAVING SELECTIVELY INTERCONNECTED COUNTER...
- Publication number 20100054013
- Publication date Mar 4, 2010
- Sachin Joshi
- G11 - INFORMATION STORAGE

Sachin Joshi

Person

Patents Grantslast 30 patents

Low power signaling for data transfer

Techniques to boost word-line voltage using parasitic capacitances

Low swing dynamic circuit

Compiling regular expressions for programmable content addressable...

Comparator circuit

Reformulating regular expressions into architecture-dependent bit g...

Power reduction in a content addressable memory having programmable...

Content addressable memory having selectively interconnected rows o...

Content addresable memory having selectively interconnected counter...

Content addresable memory having programmable interconnect structure

Content addresable memory having selectively interconnected counter...

Regular expression search engine

Content addressable memory having programmable interconnect structure

Patents Applicationslast 30 patents

TECHNIQUES TO BOOST WORD-LINE VOLTAGE USING PARASITIC CAPACITANCES

TECHNIQUES TO BOOST WORD-LINE VOLTAGE USING PARASITIC CAPACITANCES

Low Power Signaling for Data Transfer

Low Swing Dynamic Circuit

CONTENT ADDRESSABLE MEMORY HAVING PROGRAMMABLE INTERCONNECT STRUCTURE

CONTENT ADDRESSABLE MEMORY HAVING SELECTIVELY INTERCONNECTED COUNTE...

CONTENT ADDRESABLE MEMORY HAVING PROGRAMMABLE INTERCONNECT STRUCTURE

CONTENT ADDRESABLE MEMORY HAVING SELECTIVELY INTERCONNECTED COUNTER...