Sadhana Madhyastha

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Los Altos, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Word line transistor stacking for leakage control
- Patent number 6,914,848
- Issue date Jul 5, 2005
- Intel Corporation
- Shahram Jamshidi
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power precharge scheme for memory bit lines
- Patent number 6,631,093
- Issue date Oct 7, 2003
- Intel Corporation
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for low power memory bit line precharge
- Patent number 6,629,194
- Issue date Sep 30, 2003
- Intel Corporation
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-entry register cell
- Patent number 6,628,539
- Issue date Sep 30, 2003
- Intel Corporation
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing power consumption in a data storage device
- Patent number 6,341,099
- Issue date Jan 22, 2002
- Intel Corporation
- Sudarshan Kumar
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Word line transistor stacking for leakage control
- Publication number 20040252574
- Publication date Dec 16, 2004
- Shahram Jamshidi
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER PRECHARGE SCHEME FOR MEMORY BIT LINES
- Publication number 20030002382
- Publication date Jan 2, 2003
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for low power memory bit line precharge
- Publication number 20020184431
- Publication date Dec 5, 2002
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-entry register cell
- Publication number 20020181268
- Publication date Dec 5, 2002
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING