Sagar V. Reddy

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Santa Clara, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Low standby leakage implementation for static random access memory
- Patent number 11,915,745
- Issue date Feb 27, 2024
- DXCorr Design Inc.
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Inter-chip input-output (IO) for voltage-stacked near threshold com...
- Patent number 11,669,135
- Issue date Jun 6, 2023
- DXCorr Design Inc.
- Rajesh Tiruvuru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for compensating for gate leakage in a memory
- Patent number 7,515,475
- Issue date Apr 7, 2009
- Sun Microsystems, Inc.
- Sagar V. Reddy
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid dual match line architecture for content addressable memorie...
- Patent number 7,474,546
- Issue date Jan 6, 2009
- Sun Microsystems, Inc.
- Shashank Shastry
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM FOR SAVING LEAKAGE POWER IN STATIC RANDOM ACCESS MEMORY (SRA...
- Publication number 20250022491
- Publication date Jan 16, 2025
- DXCorr Design Inc.
- SUDARSHAN KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
LOW STANDBY LEAKAGE IMPLEMENTATION FOR STATIC RANDOM ACCESS MEMORY
- Publication number 20230080591
- Publication date Mar 16, 2023
- DXCorr Design Inc.
- SUDARSHAN KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
INTER-CHIP INPUT-OUTPUT (IO) FOR VOLTAGE-STACKED NEAR THRESHOLD COM...
- Publication number 20230051176
- Publication date Feb 16, 2023
- DXCorr Design Inc.
- Rajesh Tiruvuru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID DUAL MATCH LINE ARCHITECTURE FOR CONTENT ADDRESSABLE MEMORIE...
- Publication number 20080239778
- Publication date Oct 2, 2008
- Shashank Shastry
- G06 - COMPUTING CALCULATING COUNTING